Requirements-Driven Analog Verification Cockpit
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Solution Overview
Problem
Current analog verification methods lack formalized tools and flows, making it difficult to achieve comprehensive verification of complex integrated circuits, particularly in system-on-chip designs, as conventional approaches are limited in scalability and flexibility, and often rely on ad-hoc methods that cannot connect analog verification tasks effectively.
Innovation Solution
A requirements-driven analog verification flow is implemented, allowing disparate verification tasks to be integrated into an overarching closed-loop context, using a mapping structure to apply high-level verification requirements to various analog verification tasks, enabling overall control over complex verification processes and facilitating a top-down approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional cellview-based verification approaches are used, then individual analog verification tasks can be performed in isolation, but the verification process lacks scalability and cannot be easily extended to complex system-on-chip designs
Solution Approach 1:
The verification process is segmented into modular components: verification requirements are separated from verification tasks, and tasks are organized into hierarchical structures (project-level, module-level, cellview-level). This segmentation enables independent development and execution of verification tasks while maintaining overall scalability through the hierarchical organization.
Solution Approach 2:
A verification manager component is introduced as an intermediary that coordinates between high-level verification requirements and low-level verification tasks. The manager maintains a verification plan that maps requirements to tasks, enabling complex verification flows without requiring direct manual coordination between all components.
2Reliability
If ad-hoc verification methods are used, then flexibility in handling specific analog designs is maintained, but comprehensive verification of complex integrated circuits becomes difficult to achieve
Solution Approach 1:
Verification requirements are captured and formalized before the actual verification execution. A verification plan is prepared in advance that defines the complete verification strategy, mapping high-level requirements to specific tasks. This preliminary planning enables comprehensive verification while simplifying execution through automated task coordination.
Solution Approach 2:
The verification system implements feedback mechanisms that track the status of verification requirements and tasks. Progress is monitored and reported, allowing the system to adapt to changes and ensure complete verification coverage. The feedback loop between requirements, plan, and execution ensures reliability while maintaining ease of operation through automated tracking.
3Loss of information
If analog verification is performed in isolation within analog islands, then individual cellview verification is simplified, but the overall verification status of all blocks cannot be obtained
Solution Approach 1:
The verification system merges previously isolated analog verification tasks into a unified verification framework. Individual cellview verification results are aggregated and correlated with higher-level module and project verification status. This merging enables comprehensive visibility of verification status across all blocks while maintaining the modular structure that simplifies individual task execution.
Data Source
AI summary
Disclosed is an approach to implement a requirements-driven analog verification flow. Disparate islands of verification tasks are performed with individual cellviews to be set into an overarching and closed loop verification flow context for a project or a complex verification task.