Analog Verification IP Management via Cell-Based Storage
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Solution Overview
Problem
Current methods for managing verification intellectual property (IP) in analog and mixed-signal circuit designs are inadequate, leading to errors, loss of verification data, and difficulties in re-use and integration, as they require manual editing of simulator netlist files and are not compatible with hierarchical integration scenarios.
Innovation Solution
A graphical user interface-based system that allows designers to create, store, and manage verification IP within the design IP environment, enabling automatic translation and stitching of verification units with the design netlist for specific simulators, ensuring verification IP travels with the design and is co-managed with the design IP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If verification IP is stored in separate testbench files, then verification data can be manually managed, but verification IP does not travel with the design block and can be lost or get out of synch
Solution Approach 1:
The patent merges verification IP with design IP by storing verification data directly within the design block's cell data structure. This integration ensures that verification IP automatically travels with the design block when it is instantiated or copied, eliminating the problem of verification data being lost or getting out of synch with the design.
Solution Approach 2:
The patent implements automatic copying of verification IP along with design IP through the use of cell-based storage. When a design block is copied or instantiated in a hierarchical context, the associated verification data is automatically copied as part of the cell data, ensuring verification IP remains synchronized with the design without manual intervention.
2Ease of manufacture
If manual editing of netlist files is used to specify verification checks, then verification IP can be directed to simulators, but the process is error prone and requires netlist language skills
Solution Approach 1:
The patent introduces an intermediary layer between the user and the simulator netlist. A graphical user interface allows users to specify verification checks without manually editing netlist files. The system automatically translates these high-level specifications into the appropriate simulator netlist directives, eliminating the need for users to have netlist language skills while reducing errors.
Solution Approach 2:
The patent replaces the manual mechanical process of editing netlist files with an automated system. The graphical interface and automatic translation mechanism substitute for manual text editing, making verification IP creation easier and more reliable by eliminating syntax errors and manual intervention requirements.
3Ease of operation
If testbench level checks are used for verification, then GUI-based check specification is possible, but checks do not work when blocks are hierarchically integrated into different contexts
Solution Approach 1:
The patent makes verification IP universal by storing it at the design block level rather than the testbench level. This allows the same verification checks to be automatically applied whenever the design block is instantiated in any hierarchical context, whether at the top level or nested within other blocks, without requiring separate testbench configurations for each context.
Solution Approach 2:
The patent segments verification IP into modular, block-specific units that can be independently managed and automatically applied. Each design block carries its own verification data, which can be selectively instantiated based on the hierarchical context, enabling both ease of specification and broad adaptability across different integration scenarios.
4Productivity
If verification IP is stored outside the design IP, then design and verification can be managed separately, but significant confusion persists about what has been tested and under what assumptions
Solution Approach 1:
The patent combines design IP and verification IP into a unified cell-based structure. This merging ensures that verification context information, including what has been tested and under what assumptions, is automatically packaged with the design block. When design IP is reused, the associated verification information travels along, eliminating confusion about test coverage and assumptions.
Solution Approach 2:
The patent implements automatic copying of both design and verification IP together. When a design block is copied or instantiated, the associated verification data is automatically copied as part of the cell data structure, ensuring that verification context information is preserved and travels with the design IP across different projects and contexts.
Data Source
AI summary
A system, method, and computer program product for automatically providing circuit designers with verification information for analog and mixed-signal circuit designs. A graphical user interface based environment allows circuit designers to enter verification IP while simultaneously viewing the design IP in a schematic and/or layout editor window. Embodiments maintain the verification IP in a cellview similar to the separate cellviews used for schematic and layout data. Verification IP may be selectively translated into data that is directly exportable to and usable by particular analog and mixed-signal simulators. Embodiments direct design IP and verification IP to a simulator that dynamically stitches both together during circuit verification, and tangibly outputs verification results.