Analog Video Interface Calibration for Unknown Pixel Clocks

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Solution Overview

Problem

Existing methods for calibrating analogue video interfaces require prior knowledge of the video signal or display system, limiting their ability to handle unusual or non-standardized resolutions and being user-unfriendly and time-consuming.

Innovation Solution

A method and system that automatically calibrate an analogue video interface by generating a sample clock signal and determining its phase relation with the pixel clock signal, adjusting until synchronization is achieved, allowing for correct sampling without prior knowledge of the signal or system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual adjustment is used to obtain correct sample clock signal, then compatibility between host hardware and display unit is improved, but user friendliness and time consumption are worsened

Engineering Contradiction:
ImprovecompatibilityVSAvoiduser friendliness
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The display unit automatically detects the pixel clock frequency and calculates the appropriate sample clock signal without requiring manual user intervention. The system self-adjusts by analyzing the incoming video signal characteristics and configuring the clock generator accordingly, eliminating the need for operators to manually adjust settings while maintaining compatibility.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system performs preliminary detection and analysis of the video signal characteristics before establishing the display connection. By pre-detecting the pixel clock frequency and pre-calculating the sample clock parameters, the system ensures compatibility is established automatically before the user needs to interact with the device.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If DDC component is used to provide pixel information, then correct sampling is achieved, but device complexity increases

Engineering Contradiction:
Improvesampling accuracyVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention extracts the necessary pixel clock frequency information directly from the incoming video signal itself, rather than requiring separate DDC communication channels or additional information transfer mechanisms. By analyzing the timing characteristics of the video signal directly, the system obtains the required parameters without adding complex communication infrastructure.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The video signal serves multiple functions: it carries both the visual information and the timing characteristics needed for synchronization. The same signal path that delivers video content also provides the pixel clock frequency information, eliminating the need for separate dedicated information channels and reducing overall system complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If look-up table with VESA standards is used, then correct sampling is obtained, but adaptability to non-standard resolutions is reduced

Engineering Contradiction:
Improvesampling accuracyVSAvoidadaptability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

Instead of relying on fixed static lookup tables with predetermined standard resolutions, the system dynamically detects the actual pixel clock frequency of the incoming signal and calculates the appropriate sample clock parameters in real-time. This dynamic approach allows the system to adapt to any resolution, including non-standard ones, by continuously adjusting based on the detected signal characteristics rather than being constrained to pre-defined standards.

Inventive Principle:
Principle #15Dynamics

4Ease of operation

If automatic detection without prior knowledge is implemented, then ease of installation is improved, but measurement precision requirements increase

Engineering Contradiction:
Improveease of installationVSAvoidphase-relation measurement precision
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The system implements feedback mechanisms that continuously monitor the detected phase-relation between the pixel clock and sample clock signals. By using this feedback information, the system can iteratively refine its measurements and adjustments, ensuring that even though automatic detection is performed without prior knowledge, the final sampling accuracy meets the required precision standards through continuous optimization based on observed signal characteristics.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8130321B2Method and a system for calibrating an analogue video interface
Publication Date: 2012.03.06 BARCO NV
  • US8130321B2 patent drawing
  • US8130321B2 patent drawing
  • US8130321B2 patent drawing

AI summary

The invention relates to systems and methods for calibrating an analogue video interface. Due to the lack of pixel clock signal (206) information in the video-handling unit, a sample clock signal (202) needs to be generated, which should correspond with the unknown pixel clock signal (206). The types of signals transmitted to the video-handling unit may correspond with strange display formats and no up-front information may be present. The present invention provides methods and systems for automatic calibration of an analogue video interface. These are based on obtaining an analogue video signal (208) that is based on a pixel clock signal (206), generating a sample clock signal (202) having a first frequency by means of a PLL feedback divider having a value, determining a phase-relation between the video signal (208) and the sample clock signal (202) and evaluating the phase-relation to determine if the correct sample clock signal (202) is generated. The method is looped until a correct value for the PLL feedback divider is obtained so as to obtain a correct sample clock signal (202).