Analog Zero-Crossing Detection Circuit for PFC Systems
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Solution Overview
Problem
Conventional bridge PFC converters experience high conduction and switching losses due to the presence of a rectifying bridge, and existing solutions using digital processors for phase detection and zero-crossing detection introduce significant signal processing delays, affecting the accuracy of the PFC system, especially in high-frequency applications.
Innovation Solution
A control circuit that utilizes analog circuits to detect and process inductor voltage signals, generating a PWM control signal by combining signal detection, zero-crossing detection, and frequency limiting functions, thereby reducing processing delays and improving signal processing accuracy in the PFC system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital processors (DSP/MCU) are used for phase detection and zero-crossing detection, then the PFC system can achieve accurate control, but significant signal processing delays are introduced, affecting accuracy especially in high-frequency applications
Solution Approach 1:
The patent replaces the digital processor-based signal processing system with an analog circuit-based system. The analog circuit directly processes the zero-crossing detection signal through continuous voltage comparisons and operational amplifiers, eliminating the discrete sampling and computational delays inherent in digital processors. This substitution of analog for digital signal processing resolves the contradiction by providing both accuracy and real-time response without processing delays.
Solution Approach 2:
The patent introduces an intermediate analog signal processing stage between the zero-crossing detection and the final control output. This intermediate stage uses operational amplifiers and voltage comparators to condition and process the signal continuously in the analog domain, serving as a mediator that bridges the detection and control functions without the delays of digital conversion and processing.
2Loss of energy
If bridgeless PFC topology is used to reduce conduction and switching losses, then energy efficiency is improved, but the complexity of phase detection and zero-current detection increases
Solution Approach 1:
The analog circuit designed in the patent serves multiple functions simultaneously: it performs phase detection, zero-crossing detection, and signal conditioning using a unified analog processing architecture. This multi-functional approach reduces the overall system complexity compared to implementing separate detection circuits for each function, thereby resolving the contradiction between energy efficiency gains and detection circuit complexity.
Solution Approach 2:
The patent merges the phase detection and zero-crossing detection functions into a single integrated analog circuit block. By combining these detection functions that were previously handled separately (and would be even more complex in bridgeless topology) into one unified analog processing unit, the patent reduces the overall detection circuit complexity while maintaining the energy efficiency benefits of the bridgeless PFC topology.
3Measurement precision
If high-frequency ZCD signals are processed by DSP/MCU, then accurate phase detection is achieved, but the processing delay increases significantly, worsening the overall system accuracy
Solution Approach 1:
The patent replaces the digital signal processing mechanism with an analog processing mechanism that operates continuously without sampling intervals. The analog circuit processes high-frequency ZCD signals through continuous voltage comparisons and operational amplifier operations, eliminating the quantization and computational delays inherent in digital processing, thereby achieving both accuracy and minimal delay.
Solution Approach 2:
The patent performs preliminary signal conditioning and processing in the analog domain before any digital processing occurs. By pre-processing the ZCD signal through analog amplification, filtering, and level-shifting stages, the patent prepares the signal in advance so that subsequent processing (whether analog or digital) requires minimal computation time, thereby reducing overall processing delay while maintaining accuracy.
Data Source
AI summary
The present disclosure provides a control circuit, where the control circuit includes: a signal detection unit, a zero-crossing detection (ZCD) signal acquisition unit, a pulse width modulation (PWM) control signal generation unit, and a signal processing unit; where the signal detection unit, the ZCD signal acquisition unit, the PWM control signal generation unit and the signal processing unit are connected in cascade. The control circuit provided in the present disclosure reduces processing delay of a ZCD signal and improve signal a processing accuracy of a power factor correction (PFC) system.