Anchor Vias for Large Substrate Structural Vias Thermal Fatigue
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Solution Overview
Problem
Fast computing devices experience thermal fatigue due to repeated temperature changes, leading to delamination and failure of power planes and electrical wires on carrier substrates, especially in reprogrammable devices with intense computational activity.
Innovation Solution
The implementation of anchor vias with via conductors extending from the surface of a carrier substrate to secure conducting layers, providing mechanical anchoring and reducing thermal stress by matching the coefficient of thermal expansion of the substrate and conducting materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conducting layers are extended across a large area to provide sufficient power distribution, then power delivery capability is improved, but thermal stress and delamination risk increase due to repeated temperature changes
Solution Approach 1:
The patent divides the large conducting layer into multiple smaller conducting segments, each independently anchored to the substrate by its own anchor vias. This segmentation reduces the overall thermal stress on any single conducting layer portion while maintaining sufficient power distribution across the entire substrate area through the collective effect of multiple segments.
Solution Approach 2:
The patent applies anchor vias at specific strategic locations where conducting layers are most vulnerable to delamination, rather than uniformly distributing them. This localized anchoring provides targeted reinforcement at critical stress points while minimizing the overall impact on power distribution efficiency.
2Reliability
If anchor vias are used to secure conducting layers to prevent delamination, then structural reliability is improved, but manufacturing complexity increases due to additional fabrication steps
Solution Approach 1:
The patent combines the formation of anchor vias with the existing conducting layer fabrication process by depositing via conductors that serve dual purposes: filling the anchor vias for mechanical anchoring and extending to form part of the conducting layer pattern. This integration reduces the number of separate fabrication steps required.
Solution Approach 2:
The via conductors serve multiple functions simultaneously: they provide mechanical anchoring for the conducting layers, establish electrical connections, and contribute to the overall conducting layer pattern. This multi-functionality eliminates the need for separate anchor via filling and conducting layer formation steps.
3Power
If multiple conducting layers are stacked to increase power capacity, then power handling capability is improved, but thermal stress accumulation increases leading to greater delamination risk
Solution Approach 1:
The patent segments each conducting layer into multiple smaller sections with independent anchor vias, allowing each segment to expand and contract independently during thermal cycles. This reduces stress transmission between stacked layers while maintaining overall power handling capability through the cumulative effect of multiple segmented layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces thermal fatigue failure by maintaining the structural integrity of the carrier substrate laminate under thermal expansion and contraction, ensuring continued functionality even with high area coverage of conducting layers.
Implementation Method 1
matching the coefficient of thermal expansion of the substrate and conducting materials
Data Source
AI summary
An electronic package and methods by which the package reduces thermal fatigue failure of conductors in the electronic package. The electronic package includes a carrier substrate having first and second surfaces and a plurality of anchor vias having a via material extending from the first surface toward the second surface. The electronic package includes a first conducting layer having a length and a width extending laterally in two dimensions across a major part of the first surface of the carrier substrate. The anchor vias have plural attachments along the length and the width of the first conducting layer to secure the first conducting layer to the carrier substrate.