Anchored Data Conversion for Reproducible Parallel Arithmetic
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Solution Overview
Problem
Floating-point arithmetic calculations are non-associative, leading to unpredictable results when adding floating-point values in different orders, which complicates parallelization and debugging in high-performance computing environments.
Innovation Solution
The introduction of a high-precision anchored (HPA) number format, comprising a pair of a long two's complement integer and an anchor integer, allows for associative and reproducible calculations by maintaining the anchor value unchanged during additions, enabling the use of SIMD units for parallel processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If floating-point arithmetic is used for data processing, then a large range of numeric values can be represented using a finite number of bits, but calculations become non-associative leading to unpredictable results when adding values in different orders
Solution Approach 1:
The floating-point number is segmented into three distinct components: sign bit, exponent field, and significand field. This segmentation allows independent manipulation of each component during arithmetic operations, enabling the patent to control rounding and precision behavior separately for each part, thereby achieving both wide representation range and reliable associative calculations through proper rounding mode selection
Solution Approach 2:
The patent changes the rounding parameter from the default rounding-to-nearest mode to rounding-toward-zero or truncation mode for the significand. This parameter change in the rounding behavior ensures that calculations become associative by eliminating the non-deterministic rounding that occurs with rounding-to-nearest, while still maintaining the ability to represent a large range of numeric values through the exponent field
2Reliability
If floating-point additions are performed sequentially to maintain reproducibility, then calculation results become predictable, but processing speed decreases due to inability to parallelize operations
Solution Approach 1:
By changing the rounding parameter to rounding-toward-zero or truncation mode, the patent makes floating-point addition associative, which allows multiple additions to be performed in any order without affecting the result. This enables parallelization of floating-point operations using SIMD units while maintaining reproducible results, thus improving processing speed without sacrificing reliability
Solution Approach 2:
The patent introduces dynamic control over rounding modes through status register bits that can be set by instructions. This dynamic parameter adjustment allows the system to switch between different rounding behaviors as needed, enabling both sequential reproducible calculations and parallelized operations depending on the computational requirements
3Productivity
If floating-point operations are parallelized using SIMD units, then processing speed increases, but calculation results become non-deterministic due to non-associative arithmetic
Solution Approach 1:
The patent applies the parameter change of using rounding-toward-zero or truncation mode for significand operations, which makes floating-point addition associative. This allows SIMD parallelization to produce deterministic results because the associative property ensures that all parallel addition paths converge to the same result regardless of the order in which operations are performed
Solution Approach 2:
The patent copies the significand bits directly without rounding when using truncation mode, creating an exact bit-level copy that preserves associativity. This copying approach in SIMD operations ensures that parallel processing maintains determinism by eliminating the non-deterministic rounding that would otherwise occur in parallel floating-point additions
Data Source
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AI summary
An apparatus is provided, that includes an instruction decoder responsive to an anchored-data processing instruction, to generate one or more control signals. Conversion circuitry is responsive to the one or more control signals to perform a conversion from a data value to an anchored-data select value. The conversion is based on anchor metadata indicative of a given range of significance for the anchored-data select value. Output circuitry is responsive to the one or more control signals, to write the anchored-data select value to a register.