AND Double Patterning With Erasable Dummies for IC CD Control
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Solution Overview
Problem
Conventional patterning techniques face challenges in achieving consistent critical dimension (CD) control across varying pattern densities in integrated circuit (IC) manufacturing, leading to issues with etch control and transistor variation, particularly due to the limitations of optical lithography and conventional dummification methods that occupy valuable chip area and complicate routing design.
Innovation Solution
The implementation of 'AND' dual patterning, which involves creating overlaid patterns on a substrate where only the overlapping areas of multiple mask patterns result in retained features, allowing for erasable dummy features to provide improved etch control and maintain consistent CD across the IC, enabling sharp corners and uniform CDs through orthogonal patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dummification is used to improve etch control, then etch signaling is improved, but chip area is occupied and routing efficiency is degraded
Solution Approach 1:
The patent changes the state of dummy features from permanent to temporary by introducing erasable dummy features that can be removed after serving their etch control function. This allows the dummy features to provide etch signaling during fabrication and then be erased to improve routing efficiency, resolving the contradiction between etch control and routing efficiency
Solution Approach 2:
The patent extracts the harmful aspect of dummy features (occupying chip area and blocking routing) by introducing a removal step. The dummy features are taken out after they have served their purpose in providing etch control, allowing routing to proceed efficiently without the obstructive dummy structures
2Manufacturing precision
If optical lithography with sub-resolution structures is used to improve CD consistency, then pattern density variation is addressed, but etch-uniformity and end point detection are not improved
Solution Approach 1:
The patent segments the patterning process into two independent components: optical lithography for CD control and dummy features for etch control. By separating these functions, the patent allows each to be optimized independently - optical lithography handles CD consistency while the dummy features (which print on the wafer) handle etch-uniformity and end point detection
Solution Approach 2:
The patent introduces printed dummy features as an intermediary element that mediates between the optical lithography process and the etch process. These dummy features serve as a bridge that provides etch control without interfering with the optical lithography CD control, allowing both processes to work effectively together
3Adaptability or versatility
If wide pattern density is used to enable IC interconnect routing, then routing flexibility is improved, but etch control and CD precision are degraded
Solution Approach 1:
The patent applies local quality by introducing dummy features specifically in low-density areas where routing flexibility is needed. This allows wide pattern density for routing while maintaining CD precision in the actual device areas. The dummy features are placed locally where needed to provide etch control without affecting the precision of the actual transistors and interconnects
Data Source
AI summary
A method for manufacturing integrated circuit (IC) devices includes forming first and second mask patterns with overlapping and non-overlapping features. Non-overlapping features may be removed before etching a target material layer. A third mask pattern may be formed from the overlapping features and used to etch a target material layer. The third mask pattern may be employed to make regular arrays of substantially rectangular structures.An IC device may include an IC die, an array of structures on a layer of the IC die, and multiple groups of parallel stripes of indentations or depressions in the layer. The structures may each include a transistor and a capacitor.