Angled 2T Memory Cell Layout for Higher Density Arrays
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Solution Overview
Problem
Conventional 2T memory cells with planar transistors face challenges in achieving high density and low power consumption, as well as efficient electrical connectivity, due to their planar architecture, which limits their scalability and design flexibility.
Innovation Solution
Implementing 2T memory cells with angled transistors, where read and write transistors are positioned in different planes, allowing for overlapping footprints and efficient sharing of terminals, thereby increasing density and drive current while reducing transistor widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistors are used in 2T memory cells, then manufacturing is easier, but memory cell density and power consumption performance are insufficient
Solution Approach 1:
The patent transitions from planar transistors to vertically-oriented nanoribbon transistors, utilizing the third dimension (vertical channel orientation) to increase memory cell density. The nanoribbon structure stands perpendicular to the substrate, allowing higher integration density while maintaining manufacturability through established semiconductor processing techniques adapted for vertical architectures.
2Quantity of substance
If FinFETs or nanoribbon transistors are used to increase density, then memory cell density improves, but array arrangement becomes difficult
Solution Approach 1:
The memory array is segmented into modular units where each memory cell contains two nanoribbon transistors with clearly defined word line and bit line connections. This segmentation allows systematic arrangement of memory cells in regular patterns, simplifying array design and fabrication while achieving high density through the vertical nanoribbon structure.
3Area of stationary object
If transistors are arranged in overlapping footprints in different planes, then footprint area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
By orienting nanoribbon transistors vertically and arranging memory cells with overlapping footprints in different vertical planes, the patent reduces the planar footprint area. The vertical orientation allows transistors to be stacked or arranged in three-dimensional configurations, achieving area reduction while using standard semiconductor manufacturing processes that can handle the required precision.
Data Source
AI summary
IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.