Flash Memory Array with Angled Bit Lines for Low Power Programming
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Solution Overview
Problem
Conventional NOR flash memory technologies face limitations in reducing memory cell size and decreasing power consumption due to high bit line voltage requirements and inefficient programming methods, which hinder the development of high-capacity, low-cost, and low-power nonvolatile memory solutions.
Innovation Solution
A flash memory array structure where bit lines and word lines intersect at an angle other than 90 degrees, allowing two adjacent memory cells to share a source terminal and be controlled by separate word lines and bit lines, enabling a programming method with bias voltages that reduce power consumption by avoiding punch-through effects and allowing split-gate programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If channel hot electron injection method is used for programming NOR flash memory, then programming speed is improved, but power consumption increases and programming efficiency decreases
Solution Approach 1:
The bit line voltage is segmented and shared between two adjacent memory cells. Instead of applying the full high voltage (4-5V) to a single cell, the voltage is distributed across two cells, reducing the power consumption while maintaining programming capability through the coupled programming mechanism
Solution Approach 2:
Two adjacent memory cells are merged into a single programming operation. By coupling the programming of two cells that share a common source terminal, the system achieves better programming efficiency and reduced power consumption compared to programming single cells independently
2Reliability
If high bit line voltage (4-5V) is applied for channel hot electron programming, then programming capability is maintained, but channel length cannot be reduced due to punch-through phenomenon
Solution Approach 1:
The high bit line voltage is segmented and shared between two adjacent cells. Each cell experiences a reduced voltage stress, preventing the punch-through phenomenon that would occur with full high voltage applied to a single cell, thereby enabling shorter channel lengths
Solution Approach 2:
The shared source terminal acts as an intermediary that couples two adjacent cells. This coupling mechanism allows the system to maintain programming capability while distributing the voltage stress, effectively preventing punch-through in short-channel devices
3Use of energy by moving object
If split-gate programming method is used with large voltage difference between source and drain terminals, then programming efficiency is improved and power consumption is reduced, but channel shortening is limited
Solution Approach 1:
The voltage difference required for split-gate programming is segmented and distributed across two adjacent cells. This allows each cell to operate with reduced voltage stress, enabling channel shortening while maintaining the power consumption benefits of split-gate programming
Solution Approach 2:
The system preliminarily establishes a coupling relationship between two adjacent cells before programming. This preliminary coupling allows the subsequent programming operation to proceed with reduced voltage requirements, enabling further channel shortening
4Device complexity
If conventional NOR-type array with perpendicular word lines and bit lines is used, then array structure is simple, but two adjacent cells cannot be involved in programming together, limiting power consumption reduction
Solution Approach 1:
The array structure transitions from the conventional symmetric perpendicular arrangement to an asymmetric configuration where bit lines and word lines intersect at angles other than 90 degrees. This asymmetric arrangement enables the coupling of adjacent cells for combined programming while maintaining manufacturing feasibility
Solution Approach 2:
The array structure is modified by changing the angular relationship between bit lines and word lines from the conventional perpendicular (90 degrees) to non-perpendicular angles. This dimensional change in the geometric arrangement enables new programming mechanisms that couple adjacent cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces memory cell size, increases storage density, and decreases power consumption by allocating high bit line voltage across two cells and applying different voltages to word lines, thereby improving programming efficiency and reducing power usage.
Implementation Method 1
In the programming method, the electrons are accelerated in the channels of the adjacent cells, and then attracted by a vertical electric field produced by the word line voltage bias in the channel of the selected memory cells, so as to be injected into a charge storage layer.
Data Source
AI summary
The invention provides a flash memory array structure and a method for programming the same, which relates to a technical field of nonvolatile memories in ultra large scale integrated circuit fabrication technology. The flash memory array of the present invention includes memory cells, word lines and bit lines connected to the memory cells, wherein the word lines connected to control gates of the memory cells and the bit lines connected to drain terminals of the memory cells are not perpendicular to each other but cross each other at an angle; the control gates of two memory cells adjacent to each other along the channel direction between every two bit lines are controlled by two word lines, respectively, drain terminals thereof are controlled by two bit lines, respectively, and source terminals thereof are shared. The present invention also provides a method for programming the flash memory array structure, which can realize a programming with low power consumption.