Angled Channel Trench LDMOS Transistor for Low Rdson
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Solution Overview
Problem
Conventional techniques for reducing gate to drain capacitance (Cgd) in LDMOS transistors result in increased drain-to-source on-resistance (Rdson), which decreases switching speed, making it difficult to achieve fast switching in high voltage applications.
Innovation Solution
The formation of a transistor with a channel trench at an angle other than 90° with respect to the gate direction, which creates a channel parallel to the substrate surface and along the sidewalls, enhancing carrier mobility and reducing Rdson.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional techniques are used to reduce gate to drain capacitance (Cgd), then Cgd is reduced, but drain-to-source on-resistance (Rdson) increases
Solution Approach 1:
The patent introduces a channel trench at an angle θ (0° < θ < 90°) relative to the gate direction, creating a three-dimensional channel structure that extends both laterally and vertically. This angular configuration allows the channel to utilize both the lateral dimension (parallel to substrate) and vertical dimension (along sidewalls), effectively reducing capacitance while maintaining low resistance through increased channel area and optimized carrier transport paths.
Solution Approach 2:
The patent employs a composite channel structure combining lateral channel regions (parallel to substrate) and vertical channel regions (along sidewalls of the trench). This composite geometry integrates the benefits of both lateral diffusion (for low resistance) and vertical field control (for reduced capacitance), achieving superior performance compared to conventional single-geometry channels.
2Speed
If drain-to-source on-resistance (Rdson) is reduced, then switching speed increases, but gate to drain capacitance (Cgd) increases
Solution Approach 1:
The angular channel trench creates a multi-dimensional conduction path that simultaneously reduces resistance (by increasing effective channel area and providing multiple carrier paths) and reduces capacitance (by optimizing the gate-to-drain overlap geometry). The lateral component maintains low resistance while the vertical component controls capacitance, enabling fast switching without excessive capacitance.
3Shape
If channel trench is formed at 90° to gate direction, then vertical channel is created, but carrier mobility and switching performance are limited
Solution Approach 1:
The patent optimizes the channel trench orientation at an angle θ (0° < θ < 90°) rather than the conventional 90° vertical orientation. This angular configuration creates both lateral and vertical channel components, utilizing the lateral dimension to enhance carrier mobility (similar to conventional lateral channels) while maintaining vertical field control. The optimized angle balances horizontal and vertical contributions to achieve superior switching performance.
Solution Approach 2:
The patent varies the channel trench angle parameter θ from the conventional 90° to an optimized range (0° < θ < 90°). This parameter change optimizes the balance between lateral carrier transport (affecting mobility and resistance) and vertical field control (affecting capacitance and switching). The specific angle can be tuned to achieve desired performance characteristics for different application requirements.
Data Source
AI summary
A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction.