Angled Control Gate Fin Structure for Non-Volatile Memory Integration
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Solution Overview
Problem
Conventional non-volatile memory devices using fin-FETs with SOI substrates face integration limitations due to interference between neighboring bit lines, which restricts the reduction of distance between fins and increases in integration capacity.
Innovation Solution
A non-volatile memory device with a semiconductor substrate featuring vertically protruding fins, a control gate electrode extending on an angle, gate insulating layers, storage node layers, and a buried insulating layer, which reduces interference by increasing the distance between bit lines and enhancing integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between fins is reduced to increase integration, then integration capacity is improved, but interference between neighboring bit lines increases during erasing operations
Solution Approach 1:
The control gate electrode is extended onto the top portions of the fins at an angle (e.g., 45 degrees) rather than being strictly lateral, utilizing the vertical dimension to increase separation between adjacent bit line structures. This angular extension creates additional spatial separation in the vertical-z plane, reducing capacitive coupling and interference between neighboring fins while maintaining horizontal integration density.
Solution Approach 2:
A buried insulating layer is introduced between the fins and filled with material having a low dielectric constant (k-value). This intermediary layer acts as a shield that reduces the electric field coupling between adjacent bit lines during erasing operations, thereby minimizing interference while allowing the fins to remain in close proximity for high integration.
2Reliability
If SOI substrates are used to improve short channel effects, then device performance is improved, but substrate cost increases
Solution Approach 1:
The invention uses bulk semiconductor substrates with sacrificial oxide layers instead of expensive SOI substrates. The sacrificial oxide is selectively removed to form suspended fin structures, achieving SOI-like short channel effect control in a cost-effective manner using standard bulk substrate processing techniques.
3Object-affected harmful factors
If the control gate electrode extends onto top portions of fins at an angle, then interference between bit lines is reduced, but device structure complexity increases
Solution Approach 1:
The control gate electrode structure is merged with the fin structure by extending the same conductive material continuously from the lateral gate region onto the top portions of the fins at an angle. This integrated formation process using single crystalline or polysilicon layers reduces structural complexity compared to adding separate components, while still achieving the interference reduction benefit.
Data Source
AI summary
A non-volatile memory device and a method of fabricating the same are provided. A non-volatile memory device may include a semiconductor substrate including a body and at least one pair of fins vertically protruding from the body and spaced apart from each other, and at least one control gate electrode on at least portions of outer side surfaces of the at least one pair of fins and extending onto top portions of the at least one pair of fins on an angle with the at least one pair of fins. The non-volatile memory device may further include at least one pair of gate insulating layers between the at least one control gate electrode and the at least one pair of fins, and at least one pair of storage node layers between the at least one pair of gate insulating layers and at least a portion of the at least one control gate electrode. The at least one control gate electrode may extend onto top portions of the at least one pair of fins in a zigzag fashion.