Angled Vertical Die Group Layout for Stress-Resistant Packaging
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Solution Overview
Problem
Semiconductor dies with different coefficients of thermal expansion can lead to delamination, dishing on bonding pads, deformation, and warpage in stacked die assemblies, due to mechanical and thermal stresses.
Innovation Solution
The solution involves arranging multiple die groups in a multi-die structure such that the top die groups are disposed sideways on a base substrate structure, with their edges bonded to provide mechanical and electrical connections. This arrangement reduces stress accumulation by aligning the die groups at angles greater than zero degrees with respect to the crystalline lattice planes of the base substrate, thereby preventing die cracking and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor dies with different coefficients of thermal expansion are assembled into a stacked die assembly, then high performance and multi-functionality are achieved, but mechanical and thermal stresses cause delamination, dishing on bonding pads, deformation, and warpage
Solution Approach 1:
The patent divides the stacked die assembly into multiple die groups, where each die group contains multiple semiconductor dies arranged in a stack. This segmentation allows the assembly to be organized into modular units that can better manage thermal and mechanical stresses through the lattice shift arrangement, reducing delamination and warpage while maintaining multi-functionality.
Solution Approach 2:
The patent introduces a lattice shift arrangement where adjacent die groups are offset from each other in the lateral direction, creating an asymmetric structure. This asymmetry prevents stress concentration and warpage by distributing thermal expansion forces more evenly across the assembly, thereby improving structural integrity while preserving the multi-functional capabilities of the stacked dies.
2Adaptability or versatility
If semiconductor dies are manufactured separately due to different processing requirements, then each die can be optimized for its specific function, but the assembly process becomes complex and stress management becomes difficult
Solution Approach 1:
The patent organizes separately manufactured semiconductor dies into die groups, where each die group serves as a modular unit. This segmentation simplifies the assembly process by allowing pre-fabricated die groups to be stacked and interconnected in a systematic manner, reducing overall assembly complexity while maintaining the functional optimization benefits of separately manufactured dies.
Solution Approach 2:
The patent implements a nested structure where multiple dies are stacked within each die group, and multiple die groups are then stacked to form the complete assembly. This nesting approach allows for hierarchical organization that simplifies manufacturing and assembly by breaking down the complex multi-die integration into manageable stages, while preserving the functional optimization of individually manufactured dies.
3Reliability
If die groups are arranged in a lattice shift pattern with non-zero angles relative to crystalline lattice planes, then stress accumulation is reduced and warpage is prevented, but the alignment and bonding process becomes more challenging
Solution Approach 1:
The patent employs asymmetric positioning of adjacent die groups by introducing a lattice shift arrangement where die groups are offset at non-zero angles relative to the crystalline lattice planes of the base substrate. This asymmetric arrangement effectively distributes thermal and mechanical stresses, preventing warpage and improving reliability, while the offset pattern provides clear alignment guidelines that can facilitate the bonding process.
Solution Approach 2:
The patent modifies the alignment parameters by introducing specific offset distances and angles between adjacent die groups in the lattice shift pattern. By changing these geometric parameters from traditional zero-angle alignment to non-zero angles, the patent achieves better stress distribution while the defined parameter values can be incorporated into manufacturing specifications to maintain precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces mechanical and thermal stresses in the substrate, preventing die breakage, cracking, and warpage, while enhancing electrical connections and system integration in stacked die assemblies.
Implementation Method 1
a first bonding member having a first edge surface substantially flush with a planar side surface of the first die group, and a second bonding member having a second edge surface substantially flush with a planar side surface of the second die group
Data Source
AI summary
A method of fabricating a semiconductor package includes: providing a first die group including a plurality of first dies stacked parallel to a front surface of the first die group; providing a second die group including a plurality of second dies parallel to a front surface of the second die group; providing a base substrate structure comprising a substrate characterized by a lattice crystalline plane extending in a third direction; bonding the first die group on the base substrate structure, wherein the first edge extends in a first direction, and the first direction and the third direction define a first angle; and bonding the second die group on the base substrate structure, wherein the second edge extends in a second direction, and the second direction and the third direction define a second angle, and at least one of the first angle and the second angle is not zero.