Angled Dopant Implant for Split Gate Flash Memory Cells
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Solution Overview
Problem
In split gate non-volatile flash memory cells, the lateral diffusion of P-type dopants from the select gate channel into the floating gate channel during thermal cycles leads to non-uniform dopant distribution, affecting the threshold voltage and read performance.
Innovation Solution
Implanting dopants into the WL channel region at an angle less than 90 degrees after the formation of the select gate, minimizing diffusion into the FG channel region, thereby maintaining uniform dopant distribution and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type dopant is implanted into the WL channel portion after floating gate and control gate formation, then the word line threshold voltage is maintained at desired levels, but the dopant diffuses laterally into the FG channel during thermal cycles, causing non-uniform dopant distribution and affecting FG transistor threshold voltage
Solution Approach 1:
The patent performs the P-type dopant implantation into the WL channel portion after the floating gate and control gate have been formed, but before the select gate is formed. This timing ensures that the dopant is already in place to maintain the desired word line threshold voltage before subsequent processing steps occur
Solution Approach 2:
The patent applies P-type dopant implantation specifically to the WL channel portion of the channel region, creating a localized doping region underneath the select gate. This local doping approach allows independent control of WL and FG channel characteristics without uniformly affecting the entire channel region
2Productivity
If the oxide layer thickness under the select gate is minimized to increase read performance, then read performance is improved, but dopant diffusion into the FG channel becomes more significant
Solution Approach 1:
The P-type dopant implantation is performed at a specific stage in the manufacturing process - after the floating gate and control gate are formed but before the select gate is formed. This preliminary timing ensures proper dopant placement to maintain WL threshold voltage while minimizing subsequent diffusion issues
Solution Approach 2:
The implantation is targeted specifically at the WL channel portion underneath the select gate, creating localized P-type doping. This local quality approach ensures that the dopant concentration is increased where needed for WL threshold voltage control without uniformly affecting the FG channel region
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures better on/off read current window, improved endurance, simplified retention screen testing, and lower manufacturing costs by preserving low and uniform FG threshold voltage.
Implementation Method 1
implanting, after the forming of the floating gate and the select gate, a dopant into a portion of the channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate
Data Source
Figure 1
Figure 2~3A
Figure 3B~3C
AI summary
A method of forming a memory cell includes forming a conductive floating gate over the substrate, forming a conductive control gate over the floating gate, forming a conductive erase gate laterally to one side of the floating gate and forming a conductive select gate laterally to an opposite side of the one side of the floating gate. After the forming of the floating and select gates, the method includes implanting a dopant into a portion of a channel region underneath the select gate using an implant process that injects the dopant at an angle with respect to a surface of the substrate that is less than ninety degrees and greater than zero degrees.