Angled End-Cap Implantation in NEDMOS/LDMOS to Cut Edge Leakage

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Solution Overview

Problem

Conventional NEDMOS and LDMOS FETs suffer from significant current leakage due to parasitic edge transistors, leading to increased standby power consumption and overall power consumption in electronic devices.

Innovation Solution

The implementation of end-cap body contact regions with angled dopant implantation in MOSFET-based ICs, which modifies the threshold voltage and reduces leakage current by extending the body contact region underneath the gate structure, thereby mitigating the effects of parasitic edge transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional NEDMOS and LDMOS FET structures are used, then high drain voltage handling capability is achieved, but significant current leakage occurs due to parasitic edge transistors

Engineering Contradiction:
Improvehigh drain voltage handling capabilityVSAvoidcurrent leakage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by modifying only the edge regions of the FET structure with angled dopant implantation, while leaving the central channel region unchanged. This creates localized P-type regions at the edges that suppress parasitic transistor formation without affecting the main channel's high voltage handling capability

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The angled dopant implantation acts as an intermediary mechanism that introduces P-type material into the edge regions through a controlled geometric process. This intermediary action creates a transition zone that suppresses leakage while maintaining the N-type drift region's voltage blocking capability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of energy

If end-cap body contact regions with angled dopant implantation are implemented, then leakage current is reduced, but device complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoiddevice complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent changes the implantation angle parameter from the conventional vertical (90 degrees) to an angled configuration (typically 45-60 degrees). This parameter change modifies the dopant distribution profile to achieve edge suppression while using the same fundamental implantation process, thereby reducing complexity compared to adding entirely new process steps

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The dopant implantation process is segmented into distinct angular orientations - vertical implantation for the main channel and angled implantation for the edge regions. This segmentation allows independent optimization of each region's electrical characteristics without requiring complete process redesign

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in MOSFETs capable of handling high drain voltages with low leakage current, improving reliability, power consumption, and performance in analog and digital circuitry, especially in RF and mmWave applications.

Implementation Method 1

implanting a first dopant at an angle from the vertical in the range of about 5° to about 60° within the end-cap body contact regions and within a first side of a conductive layer

Methodology Applied
Scientific EffectDopant implantation: Ion Implantation

Data Source

PatentUS20250098286A1Reduction of Edge Transistor Leakage on N-Type EDMOS and LDMOS Devices
Publication Date: 2025.03.20 MURATA MFG CO LTD
  • US20250098286A1 patent drawing
  • US20250098286A1 patent drawing
  • US20250098286A1 patent drawing

AI summary

MOSFET-based IC architectures, including SOI NEDMOS ICs and bulk semiconductor LDMOS ICs, that mitigate or eliminate the problems of edge transistors. One IC embodiment includes end-cap body contact regions angle-implanted to have a first characteristic (e.g., P+), a drift region, and a gate structure partially overlying the end-cap body contact regions and the drift region and including a conductive layer having a third characteristic (e.g., N+) and a first side angle-implanted to have the first characteristic. Steps for fabricating such an IC include implanting a dopant at an angle in the range of about 5° to about 60° within the end-cap body contact regions and within the first side of the conductive layer in a region of the gate structure overlying the end-cap body contact regions, wherein the angle-implanted dopant results in the first characteristic for the end-cap body contact regions and the first side of the conductive layer.