Angled Gate Cut Layout for Frontside and Backside Gate Contacts
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Solution Overview
Problem
The manufacturing of backside BEOL networks in semiconductor IC devices is challenging due to the need for multi-layer components to connect backside wires with active devices, particularly in connecting a backside contact to a backside gate or electrode.
Innovation Solution
The semiconductor IC device incorporates an angled gate cut region that separates first and second gates, allowing for a frontside gate contact and a backside gate contact to be connected effectively, thereby facilitating the integration of both frontside and backside BEOL networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a backside BEOL network is implemented to reduce routing congestion and enable device scaling, then routing efficiency and device density are improved, but manufacturing complexity increases due to the need for multi-layer components to connect backside contacts to gates
Solution Approach 1:
The patent introduces a backside BEOL network that utilizes the third dimension (backside of the substrate) for routing, allowing power and signal distribution without increasing planar footprint. This enables additional routing layers to be formed on the backside, improving routing efficiency while maintaining device density.
Solution Approach 2:
The gate structure is segmented into frontside and backside portions, with the backside gate extension providing a separate connection point for backside contacts. This segmentation allows independent optimization of frontside and backside routing paths, reducing manufacturing complexity by enabling separate processing streams.
2Productivity
If the pitch between transistors is reduced to enable further scaling, then device density increases, but the surface area available for gate contacts decreases
Solution Approach 1:
The gate connection is extended into the vertical dimension by creating a backside gate extension that protrudes from the gate structure. This allows gate contacts to be formed on the backside of the gate, providing additional contact surface area without increasing the planar pitch between transistors, thereby enabling further device scaling.
Solution Approach 2:
The gate contact function is segmented between frontside contacts (for frontside BEOL connection) and backside contacts (for backside BEOL connection). This segmentation distributes the contact requirements across different surfaces, ensuring adequate surface area is available for each contact type even as pitch is reduced.
3Adaptability or versatility
If multi-layer components are used to connect backside contacts to gates, then connectivity is achieved, but fabrication difficulty increases
Solution Approach 1:
The backside gate extension is formed as part of the gate structure fabrication process, before the backside BEOL layers are deposited. This preliminary formation of the extension structure simplifies subsequent manufacturing steps by providing a pre-positioned connection point, reducing the complexity of integrating multi-layer components.
Solution Approach 2:
The backside gate extension acts as an intermediary structure that bridges the gate and the backside BEOL network. This intermediate element simplifies the connection by providing a dedicated interface point, reducing the need for complex multi-layer routing and making the fabrication process more manageable.
Data Source
AI summary
A semiconductor integrated circuit (IC) device that includes an angled gate cut region, a first transistor associated with a first gate, and a second transistor associated with a second gate. The angled gate cut region may be angled such that its top surface area is nearest a boundary of the first transistor and its bottom surface area is nearest a boundary of the second transistor. The angled gate cut region may separate the first gate from the second gate and may further separate the source/drain regions of the first transistor from the source/drain regions of the second transistor. The angled gate cut region may provide for adequate frontside surface area of the first gate to which a frontside gate contact may connect and may further provide for adequate backside surface area of the second gate to which a backside gate contact may connect.


