Angled Shared Gate Connector for Low-Resistance Stacked FETs
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Solution Overview
Problem
Nanosheet technology faces challenges in forming a shared gate contact between upper and lower gates in stacked FETs due to interference as devices scale down, leading to increased resistance and performance issues.
Innovation Solution
An angled shared gate connection is introduced, forming an acute angle of 35 to 75 degrees, preferably 45 to 60 degrees, to prevent reduction in dimensions and maintain effective connectivity between the frontside and backside gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If devices are scaled down and fitted closer together, then device density increases, but interference between devices increases and shared gate contact formation becomes difficult
Solution Approach 1:
The patent transitions from a conventional vertical shared gate contact to an angled shared gate contact that extends diagonally through the bonding oxide layer. This dimensional change in the contact path allows the contact to connect frontside and backside gates while maintaining adequate lateral dimensions even when devices are closely spaced, thereby resolving the interference problem while preserving device density.
2Reliability
If a shared gate contact is formed between upper and lower gates, then electrical connectivity is achieved, but resistance increases due to dimensional reduction
Solution Approach 1:
By changing the contact orientation from vertical to angled, the patent increases the effective path length and lateral dimensions of the shared gate contact. This dimensional adjustment reduces resistance while maintaining electrical connectivity between the frontside and backside gates.
3Area of stationary object
If devices are placed closer together, then area utilization improves, but lateral dimensions of shared gate contact decrease
Solution Approach 1:
The angled configuration of the shared gate contact allows it to span across devices at an oblique angle, effectively maintaining adequate lateral dimensions even when devices are closely spaced. This dimensional strategy enables high area utilization while preserving the necessary contact dimensions for low resistance.
Data Source
AI summary
A microelectronic structure that includes a stacked FET. The stacked FET includes a frontside FET and a backside FET. The frontside FET includes a frontside gate and the backside FET includes a backside gate. A bonding oxide layer separates the frontside FET and the backside FET. An angled shared gate connection located in the bonding oxide layer that connects the frontside gate to the backside gate.