Embedded Angled Inductor Layout for High-Density IC Packages
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Solution Overview
Problem
The challenge in integrated circuit package fabrication is to create small form factor inductors with high inductance values and flexibility in design, while also simplifying the fabrication process and reducing costs.
Innovation Solution
The solution involves embedding angled inductors within a single dielectric build-up layer of the substrate package, using a semi-additive process (SAP) with only two lithography steps, which allows for higher inductance densities and greater design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional inductor fabrication methods are used, then inductors can be manufactured, but the form factor is large and fabrication complexity is high
Solution Approach 1:
The inductor trace is configured at an angle (e.g., 45 degrees) relative to the substrate, utilizing angular/dimensional configuration to increase the effective trace length within a reduced planar footprint, thereby achieving higher inductance in a smaller form factor
Solution Approach 2:
The inductor is embedded within the dielectric build-up layer of the substrate package, nesting the passive component within the existing substrate structure rather than adding it as a separate external component, reducing overall form factor and integration complexity
2Quantity of substance
If inductors are embedded in multiple dielectric layers, then inductance density increases, but fabrication process complexity increases
Solution Approach 1:
The angled configuration of the inductor trace within a single dielectric layer achieves equivalent inductance density to multi-layer configurations by utilizing the angular dimension to increase effective trace length without requiring additional dielectric layers
Solution Approach 2:
The inductor fabrication is merged with the existing semi-additive process (SAP) used for creating conductive traces on the substrate, utilizing the same lithography and plating steps to form both interconnect traces and inductor traces, thereby simplifying the overall fabrication process
Data Source
AI summary
An electronic substrate may be fabricated having a dielectric material, metal pads embedded in the dielectric material with co-planar surfaces spaced less than one tenth millimeter from each other, and a metal trace embedded in the dielectric material and attached between the metal pads, wherein a surface of the metal trace is non-co-planar with the co-planar surfaces of the metal pads at a height of less than one millimeter, and wherein sides of the metal trace are angled relative to the co-planar surfaces of the metal pads. In an embodiment of the present description, an embedded angled inductor may be formed that includes the metal trace. In an embodiment, an integrated circuit package may be formed with the electronic substrate, wherein at least one integrated circuit devices may be attached to the electronic substrate. Other embodiments are disclosed and claimed.