Angled Ion Implant Capping for Replacement Gate Formation
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Solution Overview
Problem
Conventional replacement metal gate formation techniques face issues such as transistor performance degradation due to reactive ion etch damage, increased processing steps, and larger gate line resistance, particularly in short channels, which affect leakage current and power consumption in microelectronic components.
Innovation Solution
The method involves forming trenches on a substrate, depositing a gate dielectric and work function metals, using angled ion implantation to create a capping layer that pinches off trenches, and performing an angled ion etch to recess the metals, reducing damage and processing steps while allowing for more efficient gate metal deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RIE process is used to etch away OPL in long channel, then OPL removal is achieved, but transistor performance degrades due to RIE damage
Solution Approach 1:
The patent segments the trench etching process into two distinct phases: a first RIE process that etches through the OPL layer to expose the work function metal, and a second RIE process that etches through the work function metal to the gate dielectric. This segmentation allows selective removal of OPL in different channel regions at different times, preventing premature OPL removal in long channels that would expose them to damaging RIE conditions.
Solution Approach 2:
The patent performs preliminary actions by forming dummy gates and filling trenches with OPL and work function metal before the actual trench etching process. The dummy gates are temporarily formed to protect the gate dielectric during initial processing, and the work function metal is deposited beforehand to enable selective etching. These preliminary structures are removed or modified during the segmented RIE processes to achieve the desired trench formation while protecting sensitive regions.
2Reliability
If additional lithography process is performed to protect long channel work function metal, then work function metal protection is achieved, but processing steps and cost increase
Solution Approach 1:
The patent makes the work function metal serve multiple functions: it acts as both the functional work function layer for device operation and as a protective mask during the trench etching process. The work function metal is deposited conformally across all trenches, and the segmented RIE processes selectively remove OPL and work function metal based on trench depth and geometry, eliminating the need for separate lithography steps to protect work function metal in different regions.
Solution Approach 2:
The work function metal structure serves itself by acting as its own protective mask during the etching process. The conformally deposited work function metal automatically provides the necessary protection in regions where it should remain, and the segmented RIE processes exploit the geometry and depth differences to selectively remove material without requiring external lithographic patterning to guide the protection scheme.
3Area of stationary object
If smaller space is allocated for gate W metal in short channel, then space utilization is improved, but gate line resistance increases
Solution Approach 1:
The patent applies different etching conditions to different spatial regions: in short channels, the trench etching parameters are optimized to maintain adequate gate metal fill space while still achieving complete OPL and work function metal removal, whereas in long channels, the etching is controlled to preserve work function metal where needed. This local optimization of etching parameters allows each region to have the appropriate amount of gate metal space without compromising overall device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes damage to long channels, reduces gate line resistance, and eliminates the need for additional lithography processes, enhancing the performance and reliability of microelectronic components by controlling the work function and reducing processing complexity.
Implementation Method 1
forming a capping layer over the first WF metal using an angled ion implant deposition
Implementation Method 2
performing an angled ion etch to the set of trenches, wherein the angled ion etch recesses the gate dielectric and the second WF metal within the first trench
Data Source
AI summary
Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.