Angled Plate Structure for Phase Change Memory Alignment

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Solution Overview

Problem

The fabrication and utilization of phase change memory (PCM) cells face challenges due to difficulties in alignment and pitch variations, which affect the performance and reliability of memory cells and other integrated circuit components like fuses.

Innovation Solution

The introduction of angled plate structures with offset upper edges relative to electrical interconnects, which provide a larger landing area and maintain a consistent pitch across multiple interconnects, compensating for misalignment and pitch variations, and can be used as heaters in PCM cells or fuses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional alignment methods are used for memory cell fabrication, then manufacturing process simplicity is maintained, but manufacturing precision deteriorates due to pitch variations and misalignment

Engineering Contradiction:
Improvealignment precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The angled plate structure is designed with a predetermined offset of its upper edge relative to the interconnect before fabrication variations occur. This preliminary geometric configuration compensates for expected pitch variations and misalignment, ensuring that the plate still makes reliable contact with the interconnect despite manufacturing tolerances.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The plate structure employs an asymmetric angled design where the upper edge is intentionally offset from the interconnect position. This asymmetric geometry provides tolerance compensation in one direction while maintaining precise electrical contact, resolving the contradiction between alignment precision and structural simplicity.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If larger landing area is provided for interconnect contact, then reliability is improved, but area consumption increases

Engineering Contradiction:
Improvecontact reliabilityVSAvoidlanding area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

Instead of increasing the landing area in the planar dimension, the solution transitions to the vertical dimension by angling the plate structure. The offset upper edge provides tolerance compensation vertically, allowing for a smaller planar footprint while maintaining reliable contact and improved robustness against misalignment.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If consistent pitch is maintained across multiple interconnects, then manufacturing precision is improved, but device complexity increases to compensate for alternating pitch

Engineering Contradiction:
Improvepitch consistencyVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The angled plate structure with offset upper edge serves multiple functions: it provides tolerance compensation for pitch variations, ensures reliable electrical contact, and maintains consistent spacing across multiple interconnects. This universal design approach resolves the contradiction by achieving pitch consistency without requiring complex individual adjustments for each interconnect.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9748480B2Semiconductor constructions and memory arrays
Publication Date: 2017.08.29 MICRON TECHNOLOGY INC
  • US9748480B2 patent drawing
  • US9748480B2 patent drawing
  • US9748480B2 patent drawing

AI summary

Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.