Single-Layer Redistribution Structure for Low-Warpage Semiconductor Packaging
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Solution Overview
Problem
Semiconductor packages face challenges in reducing process costs and controlling warpage while maintaining high performance and reliability, especially as they become smaller and lighter, and there is a need for efficient power supply structures.
Innovation Solution
A semiconductor package design featuring a redistribution structure with a single-layered insulating layer, including horizontal and vertical redistribution structures with tracer patterns and bonding pads, which allows for efficient metal material filling and bonding of chip connection terminals, reducing process complexity and warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layered insulating layer with horizontal and vertical redistribution structures is used, then process costs are reduced and warpage is controlled, but device complexity increases due to the need for precise tracer patterns and bonding pad arrangements
Solution Approach 1:
The redistribution structure is divided into horizontal redistribution structures and vertical redistribution structures within a single insulating layer. This segmentation allows independent optimization of each structure type, simplifying the manufacturing process while maintaining overall functionality. The horizontal structures connect bonding pads in the same layer, while vertical structures connect different layers, creating a modular approach to signal routing.
Solution Approach 2:
The tracer pattern serves as an intermediary element that extends at an angle from the first and second horizontal directions. This tracer pattern provides a reference framework that simplifies the alignment and positioning of bonding pads, reducing the complexity of precise pattern arrangement while ensuring proper electrical connections.
2Quantity of substance
If multiple semiconductor chips are arranged on the redistribution structure, then capacity and performance are improved, but warpage control becomes more difficult
Solution Approach 1:
The insulating layer is designed with different local properties: regions with horizontal redistribution structures have different mechanical characteristics than regions with vertical redistribution structures. This local quality variation allows the structure to accommodate multiple semiconductor chips with different sizes and weights, distributing stress evenly to prevent warpage while maintaining high capacity.
Solution Approach 2:
The redistribution structure uses a composite design combining conductive tracer patterns, bonding pads, and insulating material in a single layer. This composite structure provides both electrical connectivity and mechanical stability, enabling the package to support multiple chips without excessive warpage while maintaining signal integrity.
3Manufacturing precision
If the tracer pattern extends at an angle from horizontal directions, then manufacturing precision is improved for bonding pad alignment, but device complexity increases due to non-standard geometric arrangements
Solution Approach 1:
The tracer pattern is formed first as a preliminary structure that establishes the geometric framework before bonding pads are positioned. By pre-defining the angular extension from horizontal directions, the tracer pattern serves as a template that guides subsequent bonding pad placement, improving alignment precision while the pattern itself remains a simple angular extension rather than a complex shape.
Data Source
AI summary
Provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.