Angled Source/Drain Conductive Feature for Dense Nanostructure FETs
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving higher device density and performance while addressing fabrication and design issues in three-dimensional designs, such as multi-gate field effect transistors, particularly in nanostructure FETs, where further improvements are needed as transistor dimensions are scaled down.
Innovation Solution
A semiconductor device structure is developed with a stack of semiconductor layers comprising alternating first and second semiconductor layers of different etch selectivity and oxidation rates, forming nanostructure transistors with gate electrodes surrounding the channels, and employing epitaxial growth methods to create fins and source/drain epitaxial features, along with precise etching and deposition processes to define isolated channels and regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase device density, then production efficiency and cost are improved, but fabrication complexity and manufacturing difficulty increase
Solution Approach 1:
The patent segments the channel structure into multiple discrete semiconductor layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) stacked vertically. This segmentation allows each layer to be independently formed and controlled, enabling scaling to smaller dimensions while maintaining manufacturability through modular fabrication processes.
Solution Approach 2:
The patent transitions from planar two-dimensional transistor structures to three-dimensional vertically-stacked structures. By stacking multiple semiconductor layers and gate structures in the vertical dimension, the device achieves higher effective channel width and improved device density without requiring further reduction of lateral feature sizes, thus managing fabrication complexity while scaling.
2Area of stationary object
If three-dimensional designs are implemented to increase device density, then area requirements are reduced, but fabrication and design issues become more complex
Solution Approach 1:
The patent implements a nested structure where gate electrodes surround and enclose the semiconductor channel layers in a gate-all-around configuration. The first gate electrode surrounds the first semiconductor layer, the second gate electrode surrounds the second semiconductor layer, and the third gate electrode surrounds the third semiconductor layer. This nesting approach maximizes the gate control over the channel while efficiently utilizing the vertical space, thereby increasing device density without proportionally increasing design complexity.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking multiple semiconductor layers and gate structures one above another. This three-dimensional arrangement allows multiple transistor channels to occupy a smaller footprint area on the chip, effectively reducing area requirements while the standardized repeating unit structure helps manage design complexity through modularity.
3Reliability
If nanostructure FETs are used to improve performance, then device functionality is enhanced, but further improvements are needed as dimensions are scaled down
Solution Approach 1:
The patent assigns different properties to different semiconductor layers to optimize local device performance. The first semiconductor layer has a first type of semiconductor material, the second semiconductor layer has a second type of semiconductor material, and the third semiconductor layer has a third type of semiconductor material. These different material types provide different carrier mobilities and electrical characteristics, allowing each layer to be optimized for specific performance requirements while maintaining overall device functionality and scalability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This structure enhances device density and performance by enabling efficient fabrication of nanostructure transistors with improved isolation and conductivity, reducing area requirements and manufacturing costs.
Implementation Method 1
employing epitaxial growth methods to create fins and source/drain epitaxial features
Implementation Method 2
alternating first and second semiconductor layers of different etch selectivity and oxidation rates
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain region, a second source/drain region adjacent the first source/drain region, an interlayer dielectric layer disposed between the first source/drain region and the second source/drain region, and a conductive feature disposed in the interlayer dielectric layer between the first source/drain region and the second source/drain region. The conductive feature includes a first portion and a second portion extending from the first portion, and an angle is formed between the first portion and the second portion. The angle is less than about 180 degrees. The conductive feature is electrically connected to the first source/drain region.