Angled Stacked Microelectronic Packages for High Density

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Solution Overview

Problem

Conventional stacked microelectronic packages face challenges with complexity, cost, thickness, and testability, particularly in incorporating multiple chips for memory applications, necessitating a solution for reliable, thin, and economically manufacturable designs.

Innovation Solution

A stacked microelectronic assembly comprising multiple packages with dielectric elements and electrically conductive contacts, where each package includes a dielectric element with a major surface and interconnect region, and microelectronic elements with chip contacts, stacked such that planes are parallel and oriented at an angle relative to a circuit panel, enabling efficient electrical coupling and thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If multiple microelectronic packages are stacked within a package to save space, then the surface area occupied on the substrate is reduced, but the device complexity increases

Engineering Contradiction:

Improvesurface area occupied on substrateVSAvoidpackage complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar arrangement of microelectronic packages to a three-dimensional stacked configuration. Multiple packages are arranged vertically along the thickness direction of the substrate, utilizing the Z-dimension to reduce the footprint area on the substrate while maintaining electrical connectivity through vertical interconnections.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where multiple microelectronic packages are contained within a single package assembly. Each package is encapsulated with its own protective housing, and the entire stack is mounted on a common substrate, creating a hierarchical nested arrangement that consolidates multiple components into one integrated unit.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Area of stationary object

If multiple microelectronic packages are stacked within a package to save space, then the surface area occupied on the substrate is reduced, but the manufacturing cost increases

Engineering Contradiction:

Improvesurface area occupied on substrateVSAvoidmanufacturing cost

Core Design Contradiction:

Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent performs preliminary assembly and testing of individual microelectronic packages before final integration into the stacked configuration. Each package is pre-assembled with its encapsulation and contacts, allowing for standardized manufacturing processes and quality control at the package level before system-level integration, thereby reducing overall manufacturing complexity and cost.

Inventive Principle:

Principle #10Preliminary action

3Area of stationary object

If multiple microelectronic packages are stacked within a package to save space, then the surface area occupied on the substrate is reduced, but the package thickness increases

Engineering Contradiction:

Improvesurface area occupied on substrateVSAvoidpackage thickness

Core Design Contradiction:

Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent deliberately accepts increased thickness in the vertical dimension to achieve significant reduction in footprint area. The stacked configuration arranges packages along the thickness direction, transforming the space utilization strategy from two-dimensional planar layout to three-dimensional vertical stacking, which is particularly advantageous for applications where board space is premium but thickness is less constrained.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Area of stationary object

If multiple microelectronic packages are stacked within a package, then space is saved, but the testability of the assembly deteriorates

Engineering Contradiction:

Improvesurface area occupied on substrateVSAvoidtestability

Core Design Contradiction:

Area of stationary objectVSDifficulty of detecting and measuring

Solution Approach 1:

The patent introduces an intermediary substrate or interconnection layer between the stacked packages and the external testing equipment. This intermediary structure provides accessible test points and electrical pathways that allow for individual package testing and system-level characterization without requiring disassembly of the stacked configuration, thereby maintaining testability despite the compact stacked arrangement.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9728524B1Enhanced density assembly having microelectronic packages mounted at substantial angle to board

Publication Date: 2017.08.08 ADEIA SEMICON TECH LLC

AI summary

A microelectronic assembly includes a plurality of stacked microelectronic packages, each comprising a dielectric element having a major surface, an interconnect region adjacent an interconnect edge surface which extends away from the major surface, and plurality of package contacts at the interconnect region. A microelectronic element has a front surface with chip contacts thereon coupled to the package contacts, the front surface overlying and parallel to the major surface. The microelectronic packages are stacked with planes defined by the dielectric elements substantially parallel to one another, and the package contacts electrically coupled with panel contacts at a mounting surface of a circuit panel via an electrically conductive material, the planes defined by the dielectric elements being oriented at a substantial angle to the mounting surface.