Angled Power Semiconductor Terminal Sidewalls for Encapsulation Integrity

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Solution Overview

Problem

The existing coupling between terminals and encapsulation in power semiconductor devices often lacks reliability and safety, leading to potential mechanical stress and growth artifacts that impair the tightness of the encapsulation, which is critical for insulation and environmental sealing.

Innovation Solution

The power semiconductor device features a first terminal with a top layer and a base layer, where the sidewalls of these layers are angled at less than 85° or greater than 95° with respect to a horizontal plane, providing a stable and secure coupling with the encapsulation, and a method of producing such devices involves forming these angled sidewalls during the manufacturing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional terminal structures with vertical or near-vertical sidewalls are used, then the manufacturing process is simple, but the coupling between terminals and encapsulation is unreliable and mechanical stress occurs

Engineering Contradiction:
Improvecoupling reliabilityVSAvoidterminal structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The terminal structure employs asymmetric sidewall angles, with the first sidewall having an angle α between 85°-95° and the second sidewall having an angle β between 5°-15° relative to the horizontal plane. This asymmetric design creates a mechanically stable coupling configuration that prevents growth artifacts and improves encapsulation tightness while maintaining manufacturing feasibility through controlled deposition processes.

Inventive Principle:
Principle #4Asymmetry

2Reliability

If conventional terminal structures are used, then the device structure is simple, but growth artifacts occur that impair encapsulation tightness

Engineering Contradiction:
Improveencapsulation tightnessVSAvoidterminal layer structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The terminal structure implements local quality variations through different sidewall angles at different regions. The first sidewall region has angle α (85°-95°) optimized for encapsulation coupling, while the second sidewall region has angle β (5°-15°) optimized for stress distribution. This localized optimization prevents growth artifacts in critical areas without requiring complete structural redesign.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The terminal structure utilizes curved sidewalls with specific angle profiles instead of straight vertical walls. The sidewalls transition from near-vertical (α=85°-95°) at the top to more inclined (β=5°-15°) at the bottom, creating a tapered geometry that eliminates sharp corners where growth artifacts typically initiate, thereby improving encapsulation tightness.

Inventive Principle:
Principle #14Spheroidality (Curvature)

3Stress or pressure

If terminal sidewalls are angled to improve coupling, then mechanical stress is reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvemechanical stressVSAvoidsidewall angle precision
Core Design Contradiction:
Stress or pressureVSManufacturing precision

Solution Approach 1:

The invention specifies parameter ranges rather than fixed values: sidewall angle α between 85°-95° and angle β between 5°-15°. These ranges provide manufacturing tolerance that reduces precision requirements while still achieving the stress-reduction benefit. The angled configuration distributes mechanical stress more evenly across the encapsulation interface compared to vertical walls.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20230082571A1Power semiconductor device and method of producing power semiconductor device
Publication Date: 2023.03.16 INFINEON TECHNOLOGIES AG
  • US20230082571A1 patent drawing
  • US20230082571A1 patent drawing
  • US20230082571A1 patent drawing

AI summary

A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.