Angled Trace Geometry for Fan-Out Wafer Level Packaging

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Solution Overview

Problem

Conventional fan-out wafer level packaging structures face warpage and trace breaking issues due to differences in thermal expansion coefficients of various materials used in die-to-die connections.

Innovation Solution

The semiconductor device incorporates a dielectric layer with traces that connect pads on multiple dies, where the trace end portions are angled relative to the body portion, reducing stress and enhancing structural integrity by distributing thermal expansion stress more evenly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fan-out wafer level packaging structure uses multiple materials with different thermal expansion coefficients for die-to-die connection, then electrical connection between dies is achieved, but warpage and trace breaking occur due to thermal expansion differences

Engineering Contradiction:
Improveconnection reliabilityVSAvoidtrace strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The trace geometry is modified by changing the angle parameter at connection points. The trace forms an angle θ (where 0° < θ < 90°) with the normal to the die surface at the pad connection points, rather than being perpendicular. This parameter change allows the trace to accommodate thermal expansion differences while maintaining electrical connection reliability.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The trace is designed with curved or angled geometry instead of straight lines. By forming the trace at an angle θ relative to the die surface normal, the structure gains flexibility to absorb thermal stress through geometric deformation, preventing trace breaking while maintaining connection integrity.

Inventive Principle:
Principle #14Spheroidality (Curvature)

2Ease of manufacture

If conventional packaging uses straight perpendicular traces connecting dies, then manufacturing is simple, but traces break at bent portions due to thermal expansion stress

Engineering Contradiction:
Improvetrace fabrication simplicityVSAvoidtrace integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The trace angle parameter θ is optimized to balance manufacturing complexity and reliability. By selecting specific angle ranges (0° < θ < 90°), the design achieves improved trace integrity while maintaining compatibility with standard fabrication processes, avoiding the need for complex curved trace manufacturing.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If conventional design uses perpendicular trace connections to dies, then trace routing is straightforward, but warpage occurs due to differential thermal expansion

Engineering Contradiction:
Improvetrace routing complexityVSAvoidpackaging stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The angled trace geometry (0° < θ < 90°) introduces geometric flexibility that allows the packaging structure to accommodate thermal expansion differences without developing excessive warpage. The angled configuration distributes thermal stress more evenly, maintaining packaging stability while keeping trace routing relatively simple.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration significantly reduces the likelihood of trace breakage and warpage, ensuring reliable die-to-die connections and improved packaging stability.

Implementation Method 1

differences in the respective coefficients of thermal expansion of the different materials

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS9773753B1Semiconductor devices and methods of manufacturing the same
Publication Date: 2017.09.26 ADVANCED SEMICON ENG INC
  • US9773753B1 patent drawing
  • US9773753B1 patent drawing
  • US9773753B1 patent drawing

AI summary

A semiconductor device includes a first die, a second die, an encapsulant, a first dielectric layer, and at least one first trace. The first die includes a first surface and a second surface opposite to the first surface and includes at least one first pad disposed adjacent to the first surface of the first die. The second die includes a first surface and a second surface opposite to the first surface and includes at least one second pad disposed adjacent to the first surface of the second die. The first dielectric layer is disposed on at least a portion of the first surface of the first die and at least a portion of the first surface of the second die. The first trace is disposed on the first dielectric layer, which connects the first pad to the second pad, and the first trace comprises an end portion disposed adjacent to the first pad and a body portion, and the end portion extends at an angle θ1 relative to a direction of extension of the body portion.