Angled Through-Silicon Vias for Compact Microelectronic Stacking
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Solution Overview
Problem
Conventional through-silicon vias (TSVs) in microelectronic devices reduce the available space for active circuitry on semiconductor chips, increasing silicon requirements and costs, and existing interconnection methods do not adequately address the need for compact, high-density connections between complex chips in portable devices and data servers.
Innovation Solution
A microelectronic assembly with conductive elements extending through angled openings and pads, allowing for efficient electrical connections between juxtaposed semiconductor devices, reducing the need for extensive chip surface area and enabling compact, high-bandwidth interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional through-silicon vias (TSVs) are used to provide electrical connections between front and rear surfaces of semiconductor chips, then electrical interconnectivity is achieved, but the available space for active circuitry on the chip surface is reduced
Solution Approach 1:
The patent transitions from planar bond pads to three-dimensional conductive structures extending through angled openings. The conductive elements project from rear surfaces at angles to generally perpendicular surfaces, creating vertical and diagonal interconnection pathways that preserve horizontal chip surface area while achieving electrical connectivity between stacked devices.
Solution Approach 2:
The conductive elements are nested within openings formed in the semiconductor substrates. The openings extend from rear surfaces toward front surfaces, and the conductive elements are positioned within these openings to provide electrical connection without occupying additional chip surface area, effectively nesting the interconnection structure within the substrate volume.
2Reliability
If conventional TSV structures are used for interconnections, then electrical connections are established, but the physical arrangement size of chip assemblies increases
Solution Approach 1:
By utilizing vertical and angled dimensions for conductive element placement rather than horizontal expansion, the patent achieves electrical connectivity without increasing the horizontal footprint of chip assemblies. The stacked arrangement with angled conductive elements creates compact three-dimensional interconnections.
Solution Approach 2:
The conductive elements are formed and positioned within openings before final assembly of the stacked devices. This preliminary formation of interconnection structures enables subsequent stacking with precise alignment, reducing the overall assembly volume by establishing connections in advance rather than requiring larger alignment margins during assembly.
3Device complexity
If conventional bond pads are used for electrical connections, then simplicity of structure is maintained, but signal propagation delays increase due to longer interconnection paths
Solution Approach 1:
The patent replaces horizontal bond pad connections with vertical and angled conductive pathways through the substrate thickness. This dimensional change creates shorter interconnection paths for signals traveling between stacked devices, reducing propagation delays while maintaining structural simplicity through the use of direct conductive elements rather than complex routing.
Solution Approach 2:
The invention extracts the electrical connection function from the traditional bond pad location on the front surface and relocates it to conductive elements extending from the rear surface. This extraction allows signals to enter and exit the substrate at optimal points, creating more direct signal paths and reducing the distance electrons must travel between stacked devices.
Data Source
Figure 1~1A
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AI summary
A microelectronic assembly 100 is provided in which first and second electrically conductive pads 108, 106 exposed at front surfaces of first and second microelectronic elements 110, 102, respectively, are juxtaposed, each of the microelectronic elements embodying active semiconductor devices. An electrically conductive element 114 may extend within a first opening 111 extending from a rear surface 118 of the first microelectronic element 110 towards the front surface 103 thereof, within a second opening 113 extending from the first opening 111 towards the front surface 103 of the first microelectronic element 110, and within a third opening 180 extending through at least one of the first and second pads 108, 106 to contact the first and second pads. Interior surfaces 121, 123 of the first and second openings 111, 113 may extend in first and second directions relative to the front surface 103 of the first microelectronic element 110, respectively, to define a substantial angle.