Angled Via Structure for Semiconductor Contact Resistance
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Solution Overview
Problem
As semiconductor contact via (CA) critical dimensions scale, vertical resistance increases, and the top CD for via landing becomes too small, leading to high via-to-CA resistance due to potential misalignment, necessitating improved CA resistance and via connectivity.
Innovation Solution
The method involves forming a semiconductor structure with gate structures and spacers, depositing an interlevel dielectric layer, creating an undercut region in the dielectric layer to form an overhang structure, and using a silicide layer and conductive materials to enhance contact resistance and connectivity, thereby increasing the critical dimensions of the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If contact via critical dimensions are scaled down, then device integration is improved, but vertical resistance increases and via landing area becomes too small
Solution Approach 1:
The patent transitions from a conventional vertical via structure to an angled via structure that extends laterally beneath the contact. This dimensional change increases the effective via landing area and reduces vertical resistance while maintaining a small contact opening, thereby improving via connectivity without sacrificing device integration.
Solution Approach 2:
The via structure is segmented into multiple regions: an upper contact opening portion and a lower angled extension portion. This segmentation allows the via to have a small opening at the top for precise alignment while extending wider at the bottom to reduce resistance and improve connectivity to the contact region.
2Productivity
If contact via critical dimensions are scaled down, then device integration is improved, but via landing area becomes too small leading to misalignment
Solution Approach 1:
By introducing a lateral extension dimension, the via structure achieves a small opening area at the top for precise alignment while providing a larger landing area at the bottom through the angled extension, thus improving manufacturing precision via alignment.
Solution Approach 2:
The via structure has different geometries at different locations: a small circular opening at the top for precise alignment and a wider angled extension at the bottom for robust landing. This local quality variation allows the via to simultaneously satisfy alignment requirements and connectivity requirements.
3Ease of manufacture
If conventional via structures are used, then process simplicity is maintained, but vertical resistance is high and connectivity is poor
Solution Approach 1:
The patent modifies the via geometry by adding a lateral extension dimension while using standard deposition and etching processes. This dimensional change reduces vertical resistance and improves connectivity without requiring fundamentally new manufacturing techniques, thus maintaining ease of manufacture.
Solution Approach 2:
The angled via structure is formed with preliminary patterning and etching steps that create the extended geometry before contact formation. This preliminary action ensures low resistance and good connectivity are built into the structure before subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves semiconductor device performance by reducing vertical resistance and enhancing via connectivity, addressing the issues of increased resistance and small via landing dimensions.
Implementation Method 1
isotropically etching the interlevel dielectric layer exposed in the opening above a top surface of the optical planarization layer to form an undercut region in the interlevel dielectric layer below the hardmask
Implementation Method 2
depositing a silicide layer on the top surface of the exposed source/drain regions
Data Source
AI summary
A method is provided which includes forming a semiconductor substrate having one or more fins. The method includes forming over the fins a plurality of gate structures. The method includes forming gate spacers on sidewalls of the gate structure. The method includes forming a source/drain region on the semiconductor substrate between each adjacent gate spacer. The method includes depositing an interlevel dielectric layer on the source/drain regions and over the gate structures. The method includes depositing a hardmask on the interlevel dielectric layer. The method includes patterning the hardmask to form a plurality of openings and exposing the top surface of each of the source/drain regions. The method includes depositing an optical planarization layer in a portion of the openings and above the top surface of the gate structures. The method includes etching the interlevel dielectric layer in the opening to form an undercut region below the hardmask.