Layout-Dependent Anisotropic Modeling for BEOL Stress
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Solution Overview
Problem
Current semiconductor design automation techniques face challenges in accurately modeling mechanical behavior of back-end-of-line (BEOL) metal interconnects and vias due to the simplification of material properties using isotropic 'smear' methods, which fail to account for layout-specific information such as metal line directions and local pattern densities, leading to unreliable stress estimation and potential design flaws.
Innovation Solution
The implementation of a computer-implemented method that replaces isotropic material representation with layout-dependent anisotropic representation, computing anisotropic mechanical properties for each BEOL layer and region of interest by extracting geometry information from files like ITF and GDS, and calculating mechanical responses based on these properties to enhance simulation accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If isotropic smear material representation is used, then computational simplicity is maintained, but mechanical behavior modeling accuracy deteriorates due to inability to account for layout-specific information
Solution Approach 1:
The patent segments the BEOL structure into individual interconnect and via layers, evaluating each layer separately rather than using a unified isotropic model. This segmentation allows the capture of layer-specific mechanical properties and layout dependencies while maintaining computational tractability through systematic processing of each layer.
Solution Approach 2:
The patent implements local quality by computing layout-dependent anisotropic material properties for each specific layer and region of interest. The material properties vary locally based on the actual metal line directions, pattern densities, and geometric configurations in different regions, rather than using a uniform isotropic approximation throughout the entire structure.
2Ease of operation
If isotropic smear method is used, then ease of computation is maintained, but stress estimation reliability deteriorates due to loss of layout-specific information
Solution Approach 1:
The patent changes the material parameter representation from isotropic to anisotropic, and from uniform to layout-dependent. The material properties are expressed as functions of local geometric parameters extracted from layout data, such as metal line directions, pattern densities, and layer configurations, enabling accurate stress estimation while maintaining computational feasibility through parameterized models.
3Measurement precision
If layout-dependent anisotropic representation is implemented, then mechanical behavior modeling accuracy is improved, but computational complexity increases due to detailed layer-by-layer evaluation
Solution Approach 1:
The patent performs preliminary actions by extracting geometric information from layout data files (such as GDS or OASIS formats) and computing layout-dependent material properties before the actual mechanical behavior simulation. This preprocessing step organizes the complex geometric data into usable material property parameters, reducing the computational burden during the subsequent mechanical analysis phase.
4Measurement precision
If detailed layer-by-layer evaluation is performed, then stress estimation accuracy is improved, but processing time increases due to individual layer computation
Solution Approach 1:
The patent merges the geometric information extraction and material property computation steps into an integrated workflow that processes multiple layers systematically. By combining layout data parsing, geometric feature extraction, and material property calculation into a unified computational framework, the patent reduces redundant operations and optimizes processing efficiency while maintaining detailed layer-by-layer analysis accuracy.
Data Source
AI summary
Computer-implemented techniques for modeling the mechanical behavior of integrated circuits using layout-dependent material properties are disclosed. The back end of line wiring that connects an integrated circuit to a substrate undergoes stresses and strains due to many heating and cooling cycles during a chip's packaging and lifecycle. Depending on integrated circuit design style, there may be vastly different thermal profiles across the integrated circuit. The mechanical behavior caused by the thermal cycles of the wire, vias, and insulators comprising the BEOL materials is simulated. Extraction of the integrated circuit structural information, regarding the BEOL materials, yields anisotropic information. Layout-dependent material volume fractions are computed using integrated circuit structural information. Anisotropic mechanical properties are determined based on the structural information. Mechanical responses are calculated based on the anisotropic material properties and the calculated material-volume fractions.