Anisotropic Junction Formation in SOI Transistors
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Solution Overview
Problem
As semiconductor device dimensions shrink, traditional scaling techniques fail to create abrupt and shallow junctions due to transient-enhanced diffusion, leading to performance degradation and increased junction capacitance, while incorporating stress-inducing elements like eSiGe and eSiC results in further performance issues and higher series resistance.
Innovation Solution
Implementing a diffusion inhibiting species, such as carbon, in the channel region and buried insulator layer of a semiconductor-on-insulator substrate, combined with a shallow and deep transistor dopant species, to promote vertical diffusion and prevent lateral diffusion during annealing, allowing for deeper source/drain junctions with reduced halo implant and spacer size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional scaling techniques (shallower implants and reduced thermal budgets) are used to shrink device dimensions, then device pitch and gate thickness are reduced, but control of abruptness and shallowness of doping profiles is limited due to transient-enhanced diffusion
Solution Approach 1:
A carbon-based diffusion barrier layer is introduced as an intermediary between the silicon substrate and the dopant source. This barrier layer selectively prevents lateral diffusion of dopants into the channel region while allowing vertical diffusion into the source/drain regions, thereby achieving abrupt doping profiles despite transient-enhanced diffusion effects
Solution Approach 2:
The carbon barrier is applied selectively to specific regions: present in the channel area to block lateral diffusion, but absent or reduced in the source/drain regions to allow vertical dopant incorporation. This spatially varying quality enables precise control over doping profiles in different device regions
2Reliability
If halo implantation is used to mitigate short channel effects, then channel region protection from source/drain encroachment is improved, but junction capacitance and band-to-band tunneling increase due to highly doped channels
Solution Approach 1:
The carbon barrier acts as a mediator that replaces the need for heavy halo implants. By blocking lateral diffusion at the channel boundary, the barrier provides short channel control without introducing the high doping concentrations that cause increased junction capacitance and band-to-band tunneling
Solution Approach 2:
The patent converts the normally harmful transient-enhanced diffusion effect into a beneficial tool. By using a low-energy implant followed by a controlled thermal budget, the transient enhancement is directed vertically into source/drain regions while the carbon barrier prevents lateral spread, achieving both deep junctions and abrupt profiles
3Reliability
If source/drain junction depth is reduced to maintain short channel control, then lateral encroachment is prevented, but series resistance increases and stress from eSiGe/eSiC is lost
Solution Approach 1:
The patent shifts the diffusion control from lateral to vertical dimensions. By using the carbon barrier to block lateral diffusion while allowing vertical diffusion, the source/drain junctions can extend deeper vertically without encroaching laterally into the channel, thereby maintaining short channel control while reducing series resistance
Solution Approach 2:
The carbon barrier mediates between the competing requirements of deep vertical junctions for low resistance and shallow lateral junctions for short channel control. It enables the junctions to achieve greater vertical depth while maintaining abrupt lateral boundaries
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces series resistance and enables thicker silicon-on-insulator substrates, optimizing carrier mobility and preventing short channel effects, thereby enhancing device performance and power efficiency.
Implementation Method 1
performing an anneal so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region
Implementation Method 2
performing an anneal so as to diffuse the transistor dopant species in a substantially vertical direction
Data Source
AI summary
A method of forming a transistor device includes implanting a diffusion inhibiting species in a semiconductor-on-insulator substrate comprising a bulk substrate, a buried insulator layer, and a semiconductor-on-insulator layer, the semiconductor-on-insulator substrate having one or more gate structures formed thereon such that the diffusion inhibiting species is disposed in portions of the semiconductor-on-insulator layer corresponding to a channel region, and disposed in portions of the buried insulator layer corresponding to source and drain regions. A transistor dopant species is introduced in the source and drain regions. An anneal is performed so as to diffuse the transistor dopant species in a substantially vertical direction while substantially preventing lateral diffusion of the transistor dopant species into the channel region.