ANN Processor Data Stream Fault Detection via CRC and FIFO

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Artificial neural networks (ANNs) face challenges in ensuring functional safety, particularly in critical applications like autonomous vehicles, due to their complexity and susceptibility to random errors and adversarial strategies, which existing solutions do not fully address.

Innovation Solution

The development of a neural network processor incorporating multiple safety mechanisms such as redundancy by design, spatial mapping, self-tuning procedures, data stream fault detection, software-defined redundant allocation, and other safety features to enhance system-level safety and error correction capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple safety mechanisms are incorporated into the ANN processor, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvefunctional safetyVSAvoidprocessor complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The safety mechanisms are segmented into distinct functional blocks: CRC generator circuit, CRC checker circuit, FIFO memory circuit, and error flagging system. Each block performs a specific safety function independently, allowing the complex safety system to be modularized and managed through separate components rather than a monolithic complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The CRC (Cyclic Redundancy Check) mechanism serves as an intermediary safety layer between the host and the ANN processor. The CRC generator and checker circuits act as mediators that verify data integrity without requiring complex safety logic within the main processing path, thus improving reliability while keeping the core processor relatively simple.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If data stream fault detection is implemented, then measurement precision is improved, but loss of time increases

Engineering Contradiction:
Improvefault detection accuracyVSAvoidprocessing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The CRC checksum is generated in advance as data is written to the FIFO memory circuit, rather than being calculated after data retrieval. This preliminary computation allows for rapid verification when data is read, improving fault detection capability while minimizing additional processing time during critical data access operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system creates and stores a copy of the data along with its CRC checksum in the FIFO memory circuit. This copying approach allows the original data to be processed while the checksum copy is independently verified, enabling parallel operations that improve detection precision without significantly increasing overall processing time.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11221929B1Data stream fault detection mechanism in an artificial neural network processor
Publication Date: 2022.01.11 HAILO TECH LTD
  • US11221929B1 patent drawing
  • US11221929B1 patent drawing
  • US11221929B1 patent drawing

AI summary

Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.