Dual-Bank Memory Architecture for ANN Accelerator Data Alignment
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Solution Overview
Problem
Existing artificial neural network (ANN) hardware accelerators require significant power and circuit area for delay registers or flip-flop blocks to align data vectors, which increases costs and reduces efficiency, especially in mobile and power-constrained devices.
Innovation Solution
The implementation of a memory system for ANN accelerators that eliminates delay registers by using a dual-bank memory architecture with a bank selector to manage data alignment without adding complexity or area, allowing for efficient data read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay registers or flip-flop blocks are used to align data vectors in ANN hardware accelerators, then data alignment is achieved, but power consumption and circuit area increase significantly
Solution Approach 1:
The memory system is divided into multiple banks (first bank, second bank, third bank) that can be independently selected and controlled. This segmentation allows different data to be read from different banks simultaneously, enabling data alignment without requiring delay registers across the entire array.
Solution Approach 2:
A bank selector is introduced as an intermediary component that controls which memory banks are accessed for reading data. This bank selector enables flexible data alignment by selectively accessing different banks, replacing the need for delay registers that would otherwise be required to synchronize data vectors.
2Reliability
If delay registers or flip-flop blocks are used to align data vectors, then data alignment is achieved, but circuit area increases proportionally to N2-N for a square array of dimension N
Solution Approach 1:
The memory system is divided into multiple banks (first bank, second bank, third bank) that can be independently selected and controlled. This segmentation allows different data to be read from different banks simultaneously, enabling data alignment without requiring delay registers across the entire array.
Solution Approach 2:
A bank selector is introduced as an intermediary component that controls which memory banks are accessed for reading data. This bank selector enables flexible data alignment by selectively accessing different banks, replacing the need for delay registers that would otherwise be required to synchronize data vectors.
3Productivity
If convolution operations are converted to GEMM operations for efficient execution, then computational efficiency is improved, but data access and storage complexity increases
Solution Approach 1:
The memory system is divided into multiple banks (first bank, second bank, third bank) that can be independently selected and controlled. This segmentation allows different data to be read from different banks simultaneously, enabling data alignment without requiring delay registers across the entire array.
Data Source
AI summary
A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.