ANN Memory Controller Using Data Locality to Cut Latency

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Solution Overview

Problem

Conventional artificial neural network models face issues with high power consumption, heating, and bottlenecks due to low memory bandwidth and latency, leading to degraded operation performance and processor starvation.

Innovation Solution

An artificial neural network memory system that utilizes artificial neural network data locality to optimize memory operations by predicting and preparing data access requests in advance, minimizing latency and bandwidth issues through an artificial neural network memory controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory operations are performed using conventional methods without data locality optimization, then memory bandwidth and latency are insufficient, but power consumption increases and processing performance degrades

Engineering Contradiction:
Improveprocessing performanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The memory controller predicts future data access requests by analyzing data locality patterns and pre-fetches data into the buffer memory before the processor actually requests it. This preliminary action eliminates waiting time and ensures data is ready when needed, improving processing performance without increasing power consumption of the processor.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

A buffer memory is introduced as an intermediary between the main memory and the processor. The memory controller manages this buffer to store frequently accessed or predicted data, reducing the frequency of main memory accesses and thereby improving performance while managing power consumption through selective buffering.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If memory bandwidth is increased to handle large artificial neural network models, then processing performance improves, but memory latency increases and power consumption rises

Engineering Contradiction:
Improveoperation processing performanceVSAvoidmemory latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system performs preliminary data fetching by predicting future access patterns based on data locality. Data is loaded into the buffer memory in advance, so when the processor needs the data, it is already available, effectively eliminating memory latency without requiring sustained high memory bandwidth.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer memory is used to store only the specific data that is predicted to be accessed soon, based on data locality analysis. This localized caching of relevant data ensures fast access for critical operations without the overhead of maintaining high bandwidth for all memory operations.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If data is fetched from memory in real-time without prediction, then memory control is simple, but processor starvation occurs and operation performance degrades

Engineering Contradiction:
Improvememory control simplicityVSAvoidoperation performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The memory controller implements a feedback mechanism by monitoring actual data access patterns and using this information to refine its predictions of future access requests. This feedback loop enables the controller to anticipate processor needs more accurately, preventing processor starvation while maintaining relatively simple control logic based on observed patterns.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system enables the memory controller to serve itself by automatically analyzing access patterns and making prediction decisions without requiring complex external control. The controller uses the data locality information it already has to autonomously determine what data to pre-fetch, simplifying the overall control architecture while improving performance.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS20260104820A1Memory system for processing artificial neural network and control method thereof
Publication Date: 2026.04.16 DEEPX CO LTD
  • US20260104820A1 patent drawing
  • US20260104820A1 patent drawing
  • US20260104820A1 patent drawing

AI summary

According to an example of the present disclosure, a system is provided. A system may include a processor configured to output a memory control signal including an artificial neural network data locality, and a memory controller configured to receive the memory control signal from the processor and control a main memory in which data of an artificial neural network model corresponding to the artificial neural network data locality, is stored.