ANN Neuron Computation via Selective Input Pair Processing
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Solution Overview
Problem
Current technologies, including CPUs, GPUs, and FPGAs, face challenges in efficiently processing artificial neural networks (ANNs) due to high computational loads, power consumption, and programming complexities, particularly in handling massive data movements and integrating with AI frameworks.
Innovation Solution
A system and method that utilize processing units to selectively process pairs of input values and weights in ANNs, optimizing calculations by sorting and selecting pairs based on absolute values and bit positions, reducing redundant operations and power consumption, and dynamically determining when to stop calculations based on thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GPUs are used to process large ANNs to overcome throughput limitations, then computational throughput is improved, but power consumption increases excessively
Solution Approach 1:
The patent extracts and processes only the most significant pairs of input values and weights that contribute meaningfully to the neuron computation outcome. By identifying and processing a subset of critical data pairs rather than all pairs, the system achieves acceptable computational accuracy with significantly reduced processing load and power consumption.
Solution Approach 2:
The patent implements partial action by processing only a portion of the total input-value/weight pairs—specifically those with the highest absolute values—rather than performing complete computations on all pairs. This partial processing approach maintains sufficient computational accuracy while dramatically reducing the computational throughput requirement and associated power consumption.
2Productivity
If FPGAs are configured to perform parallel computations for ANNs, then computational efficiency is improved, but programming complexity increases significantly
Solution Approach 1:
The patent performs preliminary sorting of input values and weights by absolute value before processing. This pre-processing step organizes the data in advance, allowing the FPGA to simply process pairs in sorted order without requiring complex runtime decision logic, thereby reducing programming complexity while maintaining computational efficiency.
Solution Approach 2:
The patent changes the processing parameter from computing all pairs to computing only the top N pairs with highest absolute values. This parameter change simplifies the FPGA programming by establishing a clear stopping criterion based on a threshold, reducing the need for complex control logic while preserving computational efficiency through focused processing of significant pairs.
3Measurement precision
If all pairs of input values and weights are processed to ensure accurate neuron computation, then computational accuracy is improved, but computational load and processing time increase
Solution Approach 1:
The patent extracts and processes only the most significant pairs of input values and weights that contribute meaningfully to the neuron computation outcome. By identifying and processing a subset of critical data pairs rather than all pairs, the system achieves acceptable computational accuracy with significantly reduced processing time.
Solution Approach 2:
The patent changes the processing parameter from computing all pairs to computing only the top N pairs with highest absolute values. This parameter change maintains sufficient accuracy for practical applications while dramatically reducing processing time by eliminating computations on less significant pairs.
4Productivity
If standard FPGA solutions are implemented for ANN computations, then hardware-level parallel processing is achieved, but adaptability to different ANN architectures and AI frameworks is reduced
Solution Approach 1:
The patent implements a universal sorting and selective processing approach that can be applied across different ANN architectures and AI frameworks. The method of sorting pairs by absolute value and processing the top N pairs is architecture-agnostic and can be integrated into various FPGA-based ANN solutions, enhancing adaptability while maintaining parallel processing efficiency.
Data Source
AI summary
An example method for accelerating neuron computations in an artificial neural network (ANN) comprises receiving a plurality of pairs of first values and second values associated with a neuron of an ANN, selecting pairs from the plurality of pairs, wherein a count of the selected pairs is less than a count of all pairs in the plurality of pairs, performing mathematical operations on the selected pairs to obtain a result, determining that the result does not satisfy a criterion, and, until the result satisfies the criterion, selecting further pairs from the plurality, performing the mathematical operations on the selected further pairs to obtain further results, and determining, based on the result and the further results, an output of the neuron.