ANN Pooling Buffer Allocation for Low-RAM Microcontrollers
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Solution Overview
Problem
Existing artificial neural network (ANN) processing systems face inefficiencies in memory allocation and computational latency during pooling operations, particularly in hardware accelerators with limited RAM resources, leading to increased costs and complexity in handling various pooling scenarios.
Innovation Solution
A micro-controller circuit with a random-access memory (RAM) block efficiently allocates memory for pooling operations, using an output buffer to compute pooling results and avoid duplicating computations, allowing for reduced memory usage and streamlined processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional memory allocation methods are used in ANN pooling operations, then computational accuracy is maintained, but memory usage increases and device complexity rises
Solution Approach 1:
The patent inverts the traditional pooling computation approach by calculating output positions from input positions rather than the conventional method. This inversion enables precise tracking of which input elements contribute to which output elements, allowing the system to compute pooling results using only the necessary memory locations without allocating additional buffers, thus maintaining computational accuracy while minimizing memory usage
Solution Approach 2:
The patent performs preliminary calculation of output positions and dimensions before executing the pooling operation. By pre-computing the output array size and position mappings based on pooling parameters (window size, stride, padding), the system allocates exactly the necessary memory without over-allocation, preventing memory waste while ensuring sufficient space for accurate computation
2Productivity
If sufficient RAM resources are allocated for pooling operations, then processing speed is improved, but device cost and complexity increase
Solution Approach 1:
The patent implements dynamic memory allocation where the output buffer size is calculated based on actual pooling parameters (window size c, stride s, padding p) rather than using fixed or over-provisioned memory. The output dimension formula `out_size = floor((in_size - c + 2*p) / s) + 1` enables the system to adapt memory usage to the specific operation requirements, optimizing the balance between processing speed and device complexity
Solution Approach 2:
The patent changes the computational parameters by inverting the pooling calculation perspective and using precise mathematical formulas to determine output dimensions. This parameter optimization allows the system to achieve high processing speeds by ensuring sufficient memory is allocated for the computation while avoiding the overhead of complex memory management structures or additional hardware buffers
3Adaptability or versatility
If multiple buffers are allocated for different pooling scenarios, then adaptability is improved, but maintenance cost and device complexity increase
Solution Approach 1:
The patent creates a universal pooling computation method that works for all pooling scenarios (max pooling, average pooling, different window sizes, strides, and padding values) through a single inverted calculation approach. The same core algorithm and memory allocation formula handle all cases, eliminating the need for multiple specialized buffers or scenario-specific code paths, thus improving adaptability while reducing maintenance complexity
Solution Approach 2:
The patent segments the pooling operation into distinct computational phases: (1) calculating output dimensions using the formula, (2) pre-computing position mappings, and (3) executing the pooling operation. This segmentation allows the system to handle diverse pooling scenarios through a structured, modular approach that is easier to maintain and debug compared to monolithic multi-buffer solutions
Data Source
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AI summary
A method (50), comprising: providing an input array (Sin; Xin) having a array size and comprising a set of ordered indexed elements having respective ordered element indexes; providing at least one of a pooling operator (PF) having an absorbing element value and a set of pooling parameters (c, s) comprising at least one of pooling window size (c), pooling stride size (s) and pooling pad size, said pooling operator being selected from among a set of pooling operators; applying said pooling operator (PF) to said input array (Sin, Xin), comprising: performing output shape inference processing comprising computing an output buffer size of an output buffer (B3) as a function of said set of pooling parameters (c, s), providing at least one output buffer B3 having a buffer size equal to said computed output buffer size and assigning an initial value to buffer elements (B3(1), B3(2), B3(3), B3(4)) of said output buffer (B3), said initial value equal to said absorbing element of said selected pooling operator (PF), performing pooling region selection comprising determining, as a function of pooling parameters (c, s), which input elements of said input array (Xin) affect which output element of said output buffer (B3, Xout), computing a combination of said elements of output buffer (B3) with said input elements affecting it, iterating performing pooling region selection and computing a combination for elements of said input array (Xin), providing said computed output result (Xout) stored in said output buffer (B3) to a user circuit.