Annular Bus System for High-Speed Real-Time Data Transmission
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Solution Overview
Problem
Current industrial field buses, such as RS232, RS485, CAN, and network buses, fail to meet the high-speed real-time data communication requirements of static CT systems due to limitations in multipoint networking, baud rate, and hardware costs, particularly in providing a simple, high-speed, and cost-effective solution for data transmission between electrical nodes in static CT systems.
Innovation Solution
A high-speed real-time bus system with an annularly connected topological structure, comprising a master node device and multiple slave node devices, utilizing a clock channel and data channels for synchronized data transmission, with each node equipped with signal preprocessing, processing, and postprocessing modules to convert and synchronize data signals, enabling efficient data processing and communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional industrial field buses (RS232, RS485, CAN, network buses) are used for data transmission between electrical nodes in static CT systems, then the system structure is simple and hardware cost is low, but the transmission speed is insufficient and real-time performance is poor
Solution Approach 1:
The bus system is segmented into multiple independent data channels (at least two channels: first data channel and second data channel) and a separate clock channel, allowing parallel data transmission and improving overall transmission speed while maintaining manageable system complexity through modular channel design
Solution Approach 2:
The patent transitions from conventional single-channel serial communication to a multi-channel parallel communication architecture, adding the dimension of channel multiplicity to achieve higher transmission speeds without proportionally increasing system complexity
2Productivity
If high-speed data transmission is implemented using conventional buses, then transmission speed improves, but hardware cost increases and real-time performance deteriorates due to protocol overhead
Solution Approach 1:
The clock signal operates continuously to synchronize all node devices, eliminating the need for start-stop protocol handshaking and ensuring continuous useful data transmission, thereby improving productivity while reducing time loss through uninterrupted communication flow
Solution Approach 2:
A dedicated clock channel acts as an intermediary between master and slave nodes, providing continuous synchronization that eliminates protocol overhead and timing negotiation delays, thereby improving real-time response without sacrificing communication efficiency
3Speed
If additional hardware devices are added to achieve high-speed transmission, then transmission speed improves, but system cost increases and structure becomes complex
Solution Approach 1:
Each node device is designed with universal functional modules (signal preprocessing module, signal processing module, signal postprocessing module) that can handle multiple tasks including data transmission, reception, and synchronization across different channels, achieving high-speed transmission without requiring additional specialized hardware for each function
Solution Approach 2:
The patent merges the clock signal generation and data signal transmission functions into a unified bus architecture where the clock channel and data channels share the same physical medium and control structure, reducing hardware complexity while maintaining high transmission speeds through functional integration
Data Source
AI summary
Disclosed are a high-speed real-time bus system and a data processing method thereof. Each node device forms an annularly connected topological structure by means of a high-speed real-time bus; a master node device respectively sends a bus clock signal and a data signal to a slave node device of the next grade of the master node device in the topological structure by means of a clock channel and a data channel; each slave node device receives the bus clock signal and the data signal sent from the respective node device of the previous grade, performs data processing according to the bus clock signal and the data signal so as to update the data signal and sends the bus clock signal and the updated data signal to the respective node device of the next grade.