Annular Compressor Decompressor Test Circuitry
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Solution Overview
Problem
Traditional design for test (DFT) circuits in integrated circuits face congestion issues due to increased scan connection lengths with higher compression ratios, limiting the achievable compression ratio and efficiency.
Innovation Solution
The implementation of a distributed compressor-decompressor logic using annular rings of codec logic elements reduces scan connection lengths, forming an annular grid that positions scan chains within the grid, allowing for improved compression ratios and reduced test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If higher compression ratios are used in traditional DFT circuits, then compression efficiency is improved, but scan connection lengths increase causing congestion
Solution Approach 1:
The DFT circuit is divided into multiple segments arranged in an annular grid structure, with scan chains distributed across different radial positions. Each scan chain connects to the compressor/decompressor through shorter local connections rather than long global interconnects, reducing overall connection length while maintaining high compression ratios
Solution Approach 2:
The patent transitions from a traditional linear or planar arrangement to a two-dimensional annular grid configuration. Scan chains are positioned at different radial distances from the center, creating a spatial distribution that reduces connection lengths in the radial direction while allowing higher compression ratios without proportionally increasing interconnect length
2Loss of time
If higher compression ratios are implemented, then test time is reduced, but circuit congestion increases
Solution Approach 1:
The compressor and decompressor logic are segmented into multiple distributed elements arranged annularly, with each element serving a specific scan chain or group of scan chains. This segmentation reduces local congestion at any single point while achieving high overall compression ratios that reduce test time
Solution Approach 2:
Different regions of the annular grid have optimized local configurations tailored to their specific scan chain requirements. Each local compressor/decompressor element is positioned and sized to minimize local congestion while contributing to the overall high compression ratio, balancing local and global performance
3Device complexity
If scan connection lengths are reduced, then congestion is reduced, but compression ratio may be limited
Solution Approach 1:
The annular grid configuration utilizes radial and angular dimensions to position scan chains and compressor/decompressor elements. This two-dimensional arrangement allows short radial connections while maintaining the ability to achieve high compression ratios through the distributed architecture, decoupling connection length from compression ratio
Solution Approach 2:
The patent employs an annular (curved) grid structure instead of a linear or rectangular layout. This curvature allows scan chains to be positioned at optimal radial distances from the center, minimizing connection lengths while the circular topology naturally supports high compression ratios through efficient data aggregation paths
Data Source
AI summary
A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.