Annular ESD Diode Layout for Lower Junction Capacitance
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Solution Overview
Problem
Diodes in protection circuits face a challenge in reducing electrostatic capacity while maintaining ESD resistance properties, as downsizing diodes can lead to decreased ESD tolerance.
Innovation Solution
A semiconductor device design featuring a semiconductor layer with a first-conductivity-type well region and a second-conductivity-type annular impurity region, forming a pn junction that reduces electrostatic capacity while maintaining ESD current capability by optimizing the shape and placement of impurity regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the diode is downsized to reduce electrostatic capacity, then the electrostatic capacity is reduced, but the ESD resistance properties decrease
Solution Approach 1:
The impurity region is designed with an annular shape rather than a circular shape, creating an asymmetric structure that optimizes the balance between electrostatic capacity and ESD resistance. The annular configuration allows for reduced interface area with the well region, thereby reducing electrostatic capacity while maintaining ESD current capability through the concentrated impurity distribution along the circular path.
2Quantity of substance
If the diode is downsized to reduce electrostatic capacity, then the electrostatic capacity is reduced, but the ESD current capability decreases
Solution Approach 1:
The impurity region is designed with non-uniform impurity concentration distribution, with higher impurity concentration at the outer perimeter and lower concentration toward the center. This local quality variation allows the region to provide high ESD current capability at the periphery where the impurity concentration is highest, while reducing the overall interface area with the well region to minimize electrostatic capacity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces electrostatic capacity while preserving ESD resistance properties, ensuring equivalent ESD current capability to circular-shaped impurity regions, thus restraining a decrease in ESD tolerance.
Implementation Method 1
a pn junction portion is formed between the well region and the second impurity region
Implementation Method 2
electric charge is accumulated near an interface between the second impurity region and the well region
Implementation Method 3
a diode used in a protection circuit is required to reduce an electrostatic capacity... capable of restraining a decrease in ESD tolerance
Data Source
AI summary
A semiconductor device includes a semiconductor layer having a principal surface, a first-conductivity-type well region formed at a surface layer portion of the principal surface of the semiconductor layer, a first-conductivity-type first impurity region that is formed at a surface layer portion of the well region and that has an inner wall portion, and a second-conductivity-type annular second impurity region formed at the surface layer portion of the well region on a more inward side than the inner wall portion such that a pn junction portion is formed between the well region and the second impurity region.