Annular Semiconductor Fin Layout for Higher-Density Dual-Gate Devices
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to inefficiencies, necessitating improved methods for enhancing device performance and integration density.
Innovation Solution
A method involving the formation of annular semiconductor fins using a ring structure as a mask, followed by epitaxial growth of source/drain structures and silicide layers, and the creation of gate structures within and surrounding these fins to improve current control and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional manufacturing methods are used for semiconductor devices, then the manufacturing process is simpler, but the integration density and device performance are lower
Solution Approach 1:
The patent segments the gate structure into two independent gates (first gate and second gate) that can independently control different regions of the annular semiconductor fin. This segmentation enables higher integration density and performance control, though it increases manufacturing complexity compared to traditional single-gate structures.
Solution Approach 2:
The patent implements a nested structure where the first gate structure is positioned within the annular semiconductor fin and the second gate structure surrounds the annular fin. This nested arrangement maximizes space utilization and achieves high integration density while maintaining independent control of current flow through the fin.
2Ease of manufacture
If manufacturing complexity is reduced, then the manufacturing process is easier, but device performance and integration density deteriorate
Solution Approach 1:
The patent employs preliminary actions in the manufacturing process by first forming the annular semiconductor fin structure with precise dimensional control before introducing the dual gate structures. The spacers are formed beforehand to define the positions of source/drain regions and gates, ensuring high device performance while managing manufacturing complexity through structured sequencing.
Solution Approach 2:
The patent applies local quality by creating different structural characteristics in different regions: the first gate structure controls the inner region of the annular fin while the second gate structure controls the outer region. Each region is optimized with specific spacer configurations and epitaxial growth conditions to achieve high device performance.
3Productivity
If integration density is increased through complex structures, then device performance improves, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar 2D structures to three-dimensional vertical structures by forming annular semiconductor fins with significant height-to-width ratios. The dual gate structures wrap around the fin in different spatial dimensions, enabling high integration density through vertical stacking and radial arrangement rather than horizontal expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases integration density and enhances device performance by allowing independent control of current through the annular semiconductor fins, thereby improving overall semiconductor device manufacturing efficiency.
Implementation Method 1
etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin
Implementation Method 2
epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin
Implementation Method 3
epitaxially growing a top source/drain structure over the annular semiconductor fin
Data Source
AI summary
A method for preparing a semiconductor device includes forming a ring structure over a semiconductor substrate, and etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin. The method also includes epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin. The method further includes forming a first silicide layer over the first bottom source/drain structure and a second silicide layer over the second bottom source/drain structure. In addition, the method includes forming a first gate structure over the first silicide layer and a second gate structure over the second silicide layer, and epitaxially growing a top source/drain structure over the annular semiconductor fin.