Annular Semiconductor Fin Layout for Higher-Density Vertical FETs
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Solution Overview
Problem
The manufacturing and integration of semiconductor devices are complex and prone to deficiencies due to their miniaturization, leading to a need for improved manufacturing processes that enhance integration density and device performance.
Innovation Solution
A semiconductor device with an annular semiconductor fin structure is developed, featuring a first and second bottom source/drain structure, silicide layers, gate structures, and a contact structure, along with a method that includes forming ring structures, etching to create annular fins, and epitaxially growing source/drain structures, which improves current control and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional manufacturing processes are used for miniaturized semiconductor devices, then device size is reduced, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent divides the semiconductor device into multiple annular regions with distinct functionalities: a first annular region containing a first transistor type and a second annular region containing a second transistor type. This segmentation allows different manufacturing processes to be applied to different regions, simplifying the overall manufacturing complexity while maintaining miniaturization benefits
Solution Approach 2:
The patent transitions from planar device layouts to three-dimensional annular structures with vertical channels extending through multiple layers. This dimensional change enables higher integration density in a smaller footprint while maintaining manageable manufacturing processes through standardized layer-by-layer fabrication
2Quantity of substance
If integration density is increased through miniaturization, then more devices fit in smaller space, but manufacturing and integration become more complicated
Solution Approach 1:
The patent merges multiple transistor structures into a unified annular configuration where first and second transistors share common substrates, isolation structures, and interlayer dielectric layers. This merging approach increases integration density while reducing the number of discrete manufacturing steps compared to separate device fabrication
Solution Approach 2:
The patent creates universal annular structures that can accommodate different transistor types in different regions. The common annular substrate, isolation structures, and interlayer dielectric serve multiple functions across different device regions, simplifying integration processes while maintaining high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly increases integration density and enhances device performance by improving current control in vertical field effect transistors, thus addressing the complexity and deficiencies in existing semiconductor manufacturing processes.
Implementation Method 1
etching the semiconductor substrate by using the ring structure as a mask to form an annular semiconductor fin
Implementation Method 2
epitaxially growing a first bottom source/drain structure within the annular semiconductor fin and a second bottom source/drain structure surrounding the annular semiconductor fin
Data Source
AI summary
A semiconductor device includes an annular semiconductor fin over a semiconductor substrate, a first bottom source/drain structure within the annular semiconductor fin, a second bottom source/drain structure surrounding the annular semiconductor fin, a first silicide layer, a second silicide layer, a first gate structure, a second gate structure, a top source/drain structure, and a contact structure over the top source/drain structure. The first silicide layer and the second silicide layer are over the first bottom source/drain structure and the bottom second source/drain structure, respectively. The first gate structure and the second gate structure are over the first silicide layer and the second silicide layer, respectively. The contact structure includes a lower contact, a middle contact over the lower contact, and an upper contact over the middle contact. A width of the upper contact is greater than a width of the middle contact.