Annular Semiconductor Fin Vertical Transistor Structure
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Solution Overview
Problem
Current semiconductor device structures with fine patterns fabricated using photolithography face limitations in resolution and integration due to the fineness of photoresist patterns, which restrict further advancements in semiconductor device miniaturization.
Innovation Solution
A method and structure for a vertical field effect transistor with an annular semiconductor fin, involving the formation of a ring structure over a substrate, etching to create an annular fin, and subsequent formation of source/drain regions and gate structures, along with the use of sacrificial epitaxial layers and self-aligned insulating spacers to enhance device architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to fabricate fine patterns, then semiconductor device integration is achieved, but resolution limitation prevents further miniaturization
Solution Approach 1:
The patent transitions from planar 2D photolithography patterning to 3D vertical fin structures. By forming annular fins with controlled cross-sectional dimensions, the invention achieves finer effective pitch through vertical dimension control rather than relying solely on horizontal photoresist pattern resolution.
Solution Approach 2:
The semiconductor device is segmented into multiple vertical fins arranged in an annular pattern. This segmentation allows the effective active area to be increased while maintaining small individual fin dimensions, thereby achieving high integration without requiring ultra-fine single-pattern resolution.
2Productivity
If photoresist pattern fineness is increased for higher integration, then device density improves, but fabrication difficulty increases
Solution Approach 1:
The patent replaces the photolithography mechanical/optical system with a self-aligned etching process. Ring structures are formed first, then used as masks to define fin patterns through anisotropic etching, eliminating the need for ultra-fine photoresist patterning while maintaining precise dimensional control.
Solution Approach 2:
Ring structures are formed in advance before the fin patterning step. These pre-formed rings serve as self-aligned masks that automatically define the fin positions and dimensions, eliminating the need for separate alignment and patterning operations that would require ultra-fine photoresist.
3Reliability
If annular fin structure with inner and outer gates is formed, then device performance is enhanced, but structural complexity increases
Solution Approach 1:
The device structure employs nested gating where an inner gate is positioned within the annular fin and an outer gate surrounds it. This nested configuration allows both gates to control the fin channel simultaneously, enhancing device performance through multi-gate control while utilizing the natural annular geometry to minimize structural complexity.
Solution Approach 2:
The annular fin structure serves multiple functions: it defines the active channel region, provides mechanical support, and enables both inner and outer gate control. The same annular geometry that enables the device structure also facilitates the multi-gate configuration, reducing the need for additional complex structural elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of semiconductor devices with improved resolution and integration capabilities, overcoming the limitations of traditional photolithography by forming finer patterns and increasing the fin width and separation, thus enhancing device performance.
Implementation Method 1
performing an etching process to form an annular semiconductor fin under the ring structure
Implementation Method 2
selectively oxidizing the sacrificial epitaxial semiconductor layer to form a self-aligned bottom insulating spacer comprising an oxide layer
Data Source
AI summary
The present application discloses a semiconductor device structure and a method for preparing the same. The method includes forming a ring structure over a substrate; performing an etching process to form an annular semiconductor fin under the ring structure; forming a lower source/drain region on the surface of the substrate in contact with a bottom portion of the annular semiconductor fin; forming an inner gate structure in contact with an inner sidewall of the annular semiconductor fin and forming an outer gate structure in contact with an outer sidewall of the annular semiconductor fin; and forming an upper source/drain region on an upper portion of the annular semiconductor fin.