Annular LDMOS Transistor Layout for Compact High-Voltage Design
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Solution Overview
Problem
Existing LDMOS transistors occupy a large area of the chip, which increases production costs and reduces drive current efficiency due to their design, limiting their performance and scalability.
Innovation Solution
The design incorporates an annular gate dielectric layer, annular gate, annular source region, and annular isolation structures surrounding the drain region, along with a lightly doped region and sidewall spacers, to enhance channel control and reduce the short-channel effect, allowing for a more compact transistor layout while maintaining high drive current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional LDMOS transistor design with a long drifting region is used, then high breakdown voltage is achieved, but the transistor occupies a large area of the chip
Solution Approach 1:
The patent introduces an annular (ring-shaped) gate structure that controls the channel in a radial direction rather than a linear direction. This dimensional change allows the current to flow through a circular path, effectively increasing the channel length without proportionally increasing the planar area occupation. The annular isolation structures similarly utilize radial positioning to achieve better space utilization while maintaining the required drift region length for high breakdown voltage.
Solution Approach 2:
The patent employs nested annular structures where the annular gate is surrounded by annular isolation structures, which are in turn surrounded by annular source/drain regions. This nested configuration allows multiple functional regions to be concentrically arranged, maximizing the use of available space and reducing the overall footprint while maintaining the necessary drift length for high voltage operation.
2Productivity
If the transistor area is reduced to increase drive current efficiency, then area occupancy decreases, but channel control and short-channel effect management become more difficult
Solution Approach 1:
The annular gate structure provides superior channel control by controlling the channel in the radial direction. The gate electrode extends circumferentially around the channel, creating a more effective electric field distribution that enhances control over the channel current. This radial control geometry allows for better modulation of the channel with reduced short-channel effects, even when the overall device footprint is minimized.
Solution Approach 2:
The patent implements annular isolation structures positioned at specific radial locations within the drift region. These isolation structures create localized modifications to the electric field distribution, providing enhanced control over the channel characteristics in critical regions. The annular source and drain regions also provide localized doping profiles that optimize carrier injection and collection, improving drive current efficiency while maintaining channel control.
Data Source
AI summary
A lateral double diffusion metal-oxide-semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrate having a well region and a drain region in the well region. The LDMOS transistor also includes at least one drifting region in the well region and an annular source region in the drifting region surrounding the drain region. Further, the LDMOS transistor includes at least one annular isolation structure surrounding the drain region in the drifting region. Further, the LDMOS transistor also includes an annular gate dielectric layer on the well region and an annular gate on the annular gate dielectric layer.