Annular RESURF Logic Layout for High-Voltage Isolation
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Solution Overview
Problem
The existing semiconductor devices used in drive control circuits for induction motors require large areas for high withstand voltage elements, leading to increased size and complexity due to separate formation of high withstand voltage potential islands and LDMOS regions for electrical isolation.
Innovation Solution
A semiconductor device design that integrates a first logic circuit region, an annular region with a field-effect transistor and resistance, and a second logic circuit region on a semiconductor substrate, where the annular region electrically isolates the first logic circuit region from the second logic circuit region, reducing the need for separate high withstand voltage potential islands and LDMOS regions, thereby minimizing the occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high withstand voltage potential island and LDMOS region are separately formed, then electrical isolation is achieved, but device area increases
Solution Approach 1:
The patent combines the high withstand voltage potential island and LDMOS region into a single integrated structure. The LDMOS region is formed within the high withstand voltage potential island, eliminating the need for separate isolation regions between them. This merging approach maintains electrical isolation through the inherent potential difference while significantly reducing the overall device area.
Solution Approach 2:
The patent implements a nested configuration where the LDMOS region is positioned inside the high withstand voltage potential island. This nesting arrangement allows the LDMOS transistor to be surrounded by the high potential region, providing natural electrical isolation without requiring additional external isolation structures, thus minimizing the occupied area.
2Reliability
If separate isolation regions are added, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The patent merges the isolation function into the existing potential island structure. By forming the LDMOS region within the high withstand voltage potential island, the patent eliminates the need for additional separate isolation regions, thereby reducing structural complexity while maintaining effective electrical isolation through the potential difference.
Solution Approach 2:
The high withstand voltage potential island serves multiple functions: it provides the high potential reference for the logic circuit and simultaneously acts as the isolation region for the LDMOS transistor. This multi-functionality eliminates the need for dedicated isolation structures, simplifying the overall device architecture.
3Area of stationary object
If LDMOS region is integrated within potential island, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary formation of the high withstand voltage potential island before forming the LDMOS region within it. This sequential approach allows the LDMOS region to be precisely positioned within the already-defined potential island boundaries, facilitating better alignment control and reducing manufacturing precision requirements compared to simultaneous formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the overall size of the semiconductor device by eliminating the need for separate high withstand voltage potential islands and LDMOS regions, improving driving performance and suppressing leakage current while maintaining high voltage withstand capabilities.
Implementation Method 1
a predetermined level shift circuit using the characteristics of a field-effect transistor is connected to the first logic circuit
Implementation Method 2
The drain voltage is detected by detecting the current flowing through the polysilicon resistance
Implementation Method 3
the drain of the field-effect transistor is connected to a sense resistance provided in the first logic circuit
Data Source
AI summary
An RESURF region is formed so as to surround a high-potential logic region with an isolation region interposed therebetween, in which a sense resistance and a first logic circuit which are applied with a high potential are formed in high-potential logic region. On the outside of RESURF region, a second logic circuit region is formed, which is applied with the driving voltage level required for driving a second logic circuit with respect to the ground potential. In RESURF region, a drain electrode of a field-effect transistor is formed along the inner periphery, and a source electrode is formed along the outer periphery. Furthermore, a polysilicon resistance connected to sense resistance is formed in the shape of a spiral from the inner peripheral side toward the outer peripheral side.