Multilayer Anode Line Layout to Suppress Display Mura
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Solution Overview
Problem
Display devices using inorganic light-emitting diodes experience parasitic capacitance between anode lines and signal lines, leading to mura and luminance deviations during low grayscale operations, which increase power consumption and reduce lifespan.
Innovation Solution
The display device design includes anode lines connected to each other and intersected by a signal line in a different layer, with a transistor to electrically connect these lines, reducing capacitance differences and preventing mura.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anode lines and signal lines are disposed in the display area, then light-emitting elements can be driven, but parasitic capacitance is generated between the anode line and signal line causing mura in low grayscale operation
Solution Approach 1:
The patent applies dimensionality change by moving the signal line from the same plane as the anode line to a different layer (vertical dimension). The signal line is disposed in a lower layer than the anode line, transforming a 2D planar problem into a 3D spatial solution. This reduces parasitic capacitance by increasing physical separation between the anode line and signal line while maintaining electrical functionality.
2Object-affected harmful factors
If anode lines are spaced apart to reduce capacitance, then parasitic capacitance decreases, but the area occupied by anode lines increases
Solution Approach 1:
Instead of increasing horizontal spacing between anode lines (which would consume more display area), the patent utilizes the vertical dimension by disposing the signal line in a lower layer. This allows the anode lines to maintain close horizontal spacing while achieving sufficient separation from the signal line through vertical layering, thus reducing parasitic capacitance without sacrificing display area.
3Device complexity
If signal line is placed in the same layer as anode line, then routing is simpler, but parasitic capacitance causes luminance deviation and increased power consumption
Solution Approach 1:
The patent resolves the trade-off between routing simplicity and energy loss by introducing vertical layering. The signal line is routed in a lower layer, which does increase routing complexity but dramatically reduces parasitic capacitance and power consumption. The patent compensates for the increased routing complexity by providing detailed configuration guidelines for the multi-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design suppresses capacitance differences, reduces power consumption, prevents luminance deviations, and extends the lifespan of the display device by minimizing parasitic capacitance effects.
Implementation Method 1
a parasitic capacitance is generated between the anode line for applying an anode voltage to each light-emitting element and the signal line
Data Source
AI summary
A display device includes a substrate including a display area and a non-display area; a driving circuit is on the substrate in the display area; a plurality of light-emitting elements are in different layers from the driving circuit; a plurality of anode lines extending in a column direction and arranged in a row direction, wherein each of the anode line connects anode electrodes of light-emitting elements that are adjacent to each other in the column direction among the plurality of light-emitting elements; and a signal line extending in the row direction in the display area and vertically overlapping each of the plurality of anode lines at the point where it intersects the plurality of anode lines, wherein the plurality of anode lines and the signal line are disposed in different layers, wherein the signal line forms a capacitor in the overlapping portion of each of the plurality of anode lines.