Anodic Bonding Chip Arrangement for Moisture Resistance
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Solution Overview
Problem
Conventional encapsulation of power semiconductor components using organic polymer materials leads to reliability issues due to high moisture reception and mismatched thermal expansion coefficients, causing operational problems.
Innovation Solution
A chip arrangement is designed with two chips facing each other, connected by electrically conductive structures through via holes, and bonded using anodic bonding, with insulating layers to manage thermal expansion and prevent moisture ingress, utilizing silicon oxide layers for insulation and encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If organic polymer material is used for encapsulation, then ease of manufacture is improved, but reliability deteriorates due to high moisture reception and CTE mismatch
Solution Approach 1:
The patent changes the material parameter from organic polymer to inorganic carrier material (such as silicon oxide), which fundamentally alters the moisture resistance and thermal expansion properties. This parameter change resolves the contradiction by selecting a material that inherently provides both manufacturability and high reliability through its physical properties.
Solution Approach 2:
The invention uses composite structures combining inorganic carrier materials with semiconductor devices, creating a hybrid system that leverages the advantages of inorganic materials (moisture resistance, CTE matching) while maintaining ease of manufacture through established bonding processes like anodic bonding.
2Reliability
If inorganic carrier material is used for encapsulation, then reliability is improved by reducing moisture reception and CTE mismatch, but device complexity increases
Solution Approach 1:
The inorganic carrier material serves multiple functions simultaneously: it provides mechanical support, thermal management through CTE matching, moisture protection, and electrical isolation. This multi-functionality reduces the need for additional separate components, thereby managing device complexity while maintaining high reliability.
Solution Approach 2:
The inorganic carrier material acts as an intermediary between the semiconductor device and the external environment, mediating thermal expansion differences and blocking moisture ingress. This intermediary role simplifies the overall structure by consolidating multiple protective functions into a single component.
3Ease of manufacture
If conventional bonding techniques are used to connect semiconductor devices, then ease of manufacture is improved, but reliability deteriorates due to moisture ingress and thermal expansion mismatch
Solution Approach 1:
The patent changes the bonding method from conventional organic-based techniques to anodic bonding, which uses electrical current to create strong chemical bonds between inorganic materials. This parameter change in the bonding process enables reliable connections that are resistant to moisture and thermal stress.
Solution Approach 2:
The invention replaces mechanical bonding methods with an electrochemical bonding process (anodic bonding). This substitution eliminates the need for mechanical fasteners or organic adhesives, creating a more reliable bond that is resistant to moisture ingress and thermal expansion mismatch while remaining manufacturable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability of power semiconductor components by aligning thermal expansion and preventing moisture ingress, thereby improving operational stability and reducing the risk of reliability issues.
Implementation Method 1
insulating layers to manage thermal expansion and prevent moisture ingress, utilizing silicon oxide layers for insulation and encapsulation
Implementation Method 2
bonded using anodic bonding
Data Source
AI summary
Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure.