Anomaly Detection Unit for Hardware Performance Monitor Data

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Solution Overview

Problem

Multi-core processors in safety-critical systems face challenges in ensuring application isolation, determinism, and predicting execution times due to resource contention, which complicates certification and software design, especially in avionics systems, where existing Hardware Performance Monitors (HPMs) are limited in visibility and add overhead.

Innovation Solution

A method and system for real-time anomaly detection using dedicated communication with hardware performance monitors (HPMs) to classify task execution and compare against expected profiles, employing a tightly coupled hardware accelerator (TCHA) to identify and mitigate anomalies without increasing determinism risks or attack surfaces, utilizing customizable instruction sets like RISC-V for low-latency monitoring and reduced contention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Hardware Performance Monitors (HPMs) are used to monitor task execution, then visibility and detection capability are improved, but system overhead and complexity increase

Engineering Contradiction:
Improvetask execution visibilityVSAvoidmonitoring system overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a dedicated anomaly detection unit as an intermediary component that sits between the HPMs and the main processing cores. This unit专门负责收集和分析HPM数据,减轻主处理器的负担,同时提供精确的任务执行监控。通过这种中介结构,实现了高测量精度而不显著增加系统 overhead

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The monitoring function is segmented into dedicated hardware components (anomaly detection unit, HPM modules) separate from the main processing cores. This segmentation allows the monitoring tasks to be performed in parallel without interfering with core processing, reducing overall system overhead while maintaining precise measurement capabilities

Inventive Principle:
Principle #1Segmentation

2Productivity

If multiple processing cores share resources to increase throughput, then productivity is improved, but resource contention and execution time variability increase

Engineering Contradiction:
Improvesystem throughputVSAvoidexecution time determinism
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the anomaly detection unit continuously monitors HPM data from multiple cores and compares actual execution times against expected profiles. When deviations are detected, the system can trigger interrupts or take corrective actions. This feedback loop enables the system to maintain high throughput through resource sharing while compensating for execution time variability through active monitoring and correction

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system establishes expected completion profiles for tasks beforehand, creating a baseline for comparison. This preliminary action allows the anomaly detection unit to quickly identify deviations from normal execution patterns without requiring complex real-time analysis, thus maintaining determinism in safety-critical applications while allowing flexible resource sharing

Inventive Principle:
Principle #10Preliminary action

3Speed

If HPMs are tightly coupled to processor cores for real-time monitoring, then response time is improved, but attack surface and security risks increase

Engineering Contradiction:
Improveanomaly detection latencyVSAvoidsecurity vulnerability
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the anomaly detection functionality from the main processor cores and implements it as a separate, dedicated hardware unit. This unit has direct access to HPM data through secure interfaces but is isolated from the main system execution paths. By taking out the monitoring function, the system achieves real-time detection speed while minimizing the attack surface, as the detection unit operates independently with limited exposure to system vulnerabilities

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240211338A1Method and microarchitecture for anomaly detection based on hardware performance monitors
Publication Date: 2024.06.27 ROCKWELL COLLINS INC
  • US20240211338A1 patent drawing
  • US20240211338A1 patent drawing
  • US20240211338A1 patent drawing

AI summary

A method for detecting anomalies in the nominal execution of tasks in a processor system includes executing a task on the processor system, monitoring, in real time via dedicated communication means, hardware performance monitors, HPMs, of at least one resource of the processor system resulting from the execution of the task on the processor system; classifying the task based on the monitored HPMs; comparing the classified task with an expected completion profile of the task; and if the classified task deviates from the expected completion profile, then identifying an anomaly in the nominal execution of the task.