ANPC Converter Switching Control for Lower Loss and Oscillation
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Solution Overview
Problem
Existing power converter devices with Active Neutral Point Clamped (ANPC) topology face inflexible control of power semiconductor switches, leading to uncontrolled switching of fifth and sixth switches relative to first and third switches at switching times, resulting in undesirable technical outcomes.
Innovation Solution
A power converter device with a control system that synchronizes the switching of first and third power semiconductor switches based on a sinusoidal target signal and a modulation signal, while the fifth and sixth switches are controlled using pulse width modulation, ensuring they switch off before and after the main switch-off time, and utilizing silicon carbide or gallium nitride for reduced switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the fifth and sixth power semiconductor switches are controlled to switch simultaneously with the first and third switches at the zero crossing of the sinusoidal target signal, then the control is simple and follows the standard ANPC topology, but the switching becomes uncontrolled due to different switching times and control line lengths, resulting in technically undesirable outcomes
Solution Approach 1:
The control device switches off the fifth power semiconductor switch before the main switch-off time (when first and third switches are switched off) rather than simultaneously. This preliminary action prevents the uncontrolled switching problem by ensuring the fifth switch is already off before the simultaneous switching event occurs, eliminating the risk of shoot-through currents while maintaining simple control logic
2Reliability
If the fifth power semiconductor switch is switched off slightly before the main switch-off time as proposed in US 2019/0013743 A1, then switching control reliability is improved, but the control flexibility is reduced since the switching time always coincides with the zero crossing of the sinusoidal target signal
Solution Approach 1:
The invention introduces a dynamic switching strategy where the fifth power semiconductor switch can be switched off at different times relative to the main switch-off time depending on the operating conditions. The control device monitors the state of the first and third switches and adjusts the fifth switch timing dynamically - switching off before the main switch-off time when needed, or allowing simultaneous switching when conditions permit, thus achieving both reliability and flexibility
3Productivity
If multiple power semiconductor switches are switched on and off at high frequency simultaneously, then power conversion efficiency is improved, but switching losses and electrical voltage oscillations increase
Solution Approach 1:
The control device implements a switching sequence that skips the simultaneous switching of the fifth switch with the first and third switches. By switching off the fifth switch before the main switch-off event and keeping it off during the simultaneous switching of other switches, the invention avoids the harmful overlap and resulting voltage oscillations, thereby reducing switching losses while maintaining high-frequency operation for efficient power conversion
Data Source
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AI summary
The invention relates to a power converter device comprising a power converter and a control device, wherein the control device is configured to control power semiconductor switches such that - the first and third power semiconductor switches are switched on and off simultaneously, and - the second and fourth power semiconductor switches are switched on and off simultaneously, wherein the second and fourth power semiconductor switches are switched on and off in the opposite direction to the first and third power semiconductor switches, and wherein the first and third power semiconductor switches are switched off at the main switch-off times.wherein the fifth power semiconductor switch is switched off before the respective main switch-off time and is only switched on again after the respective main switch-off time, or the fifth power semiconductor switch is switched on before the respective main switch-off time and is only switched off again after the respective main switch-off time.