ANPC Semiconductor Arrangement with Segmented Switching

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Solution Overview

Problem

Semiconductor arrangements, particularly those with ANPC topology, face challenges in achieving satisfactory switching characteristics and thermal performance.

Innovation Solution

The semiconductor arrangement includes multiple controllable semiconductor main-elements connected through common nodes, with each main-element having a plurality of subcomponents, allowing for controlled switching and improved thermal management through symmetrical electrical connections and freewheeling elements, enhancing switching characteristics and thermal performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If ANPC topology is implemented in semiconductor module, then power conversion capability is improved, but switching characteristics deteriorate

Engineering Contradiction:
Improvepower conversion capabilityVSAvoidswitching characteristics
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The semiconductor module divides the power conversion function into multiple independent controllable semiconductor elements (first through fourth elements) with separate load paths. Each element can be controlled independently, allowing optimized switching characteristics for each element while collectively achieving the required power conversion capability through their combined operation in series between DC+ and DC- terminals.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If ANPC topology is implemented in semiconductor module, then power conversion capability is improved, but thermal performance deteriorates

Engineering Contradiction:
Improvepower conversion capabilityVSAvoidthermal performance
Core Design Contradiction:
Adaptability or versatilityVSTemperature

Solution Approach 1:

The module segments the power handling function across four separate controllable semiconductor elements, distributing the power conversion task and associated thermal load. This segmentation allows for better thermal management as heat generation is distributed across multiple components rather than concentrated in a single element.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Each controllable semiconductor element has its own dedicated load path and control electrode, allowing for localized optimization of thermal characteristics. The separate load paths enable independent thermal management for each element, with heat dissipation optimized according to the specific operational requirements of each semiconductor element.

Inventive Principle:
Principle #3Local quality

3Reliability

If multiple controllable semiconductor elements with separate load paths are used, then switching characteristics are improved, but device complexity increases

Engineering Contradiction:
Improveswitching characteristicsVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The module merges multiple controllable semiconductor elements into a single integrated semiconductor module structure. The first through fourth controllable semiconductor elements are combined within one module, sharing common packaging and mounting structure, which reduces overall system complexity compared to using separate discrete components while maintaining the benefits of multiple independent load paths.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3396839B1Semiconductor arrangement with controllable semiconductor elements
Publication Date: 2021.12.15 INFINEON TECHNOLOGIES AG
  • EP3396839B1 patent drawingFigure 1~2
  • EP3396839B1 patent drawingFigure 3
  • EP3396839B1 patent drawingFigure 4A~4B

AI summary

A semiconductor arrangement includes a first supply node to be connected to a first electrical potential, a second supply node to be connected to a second electrical potential and a third supply node to be connected to a third electrical potential. A first semiconductor main-element and a second semiconductor main-element, each having a control electrode and a load path, the load paths connected in series between the first supply node and the second supply node, are connected with each other via a first common node. A third semiconductor main-element and a fourth semiconductor main-element, each having a control electrode and a load path, the load paths connected in series and between the third supply node and the second supply node, are connected with each other via a second common node. The arrangement further includes a fifth semiconductor main-element having a control electrode and a load path operatively connected between the first common node and an output node, and a sixth semiconductor main-element having a control electrode and a load path operatively connected between the second common node and the output node. At least two of the controllable semiconductor main-elements each comprise a plurality of identical controllable semiconductor subcomponents, each subcomponent having a control electrode and a controllable load path, the load paths being operatively connected in parallel between the nodes between which the respective controllable semiconductor main-element is connected. In each one of the at least two of the semiconductor main-elements, the first load electrode of each respective semiconductor subcomponent is electrically connected to the respective node via an individual one of a multiplicity of separate output lines, each of the separate output lines being configured to provide identical voltage and current transfers.