Hardware-Friendly ANS Decompression Using Compact State Tables
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Solution Overview
Problem
Existing data compression techniques, such as Asymmetric Numeral Systems (ANS), are not optimized for hardware-friendly implementations on Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC), requiring a more efficient lossless compression method suitable for these platforms.
Innovation Solution
A lossless compression method using entropy encoding that involves building a decoding table with distinct symbols and dynamically determining bits to recover, allowing for efficient decoding and hardware-friendly implementation by reducing the number of encoding states and optimizing storage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If existing ANS implementations are used for data compression, then compression ratio is improved, but hardware implementation efficiency deteriorates
Solution Approach 1:
The patent transforms the state representation from arbitrary large integers to compact values in the range [0, L-1] by changing the parameter space. This parameter transformation enables efficient hardware implementation using simple arithmetic operations (addition, subtraction, multiplication by constants) while preserving the compression ratio benefits of ANS encoding.
Solution Approach 2:
The patent applies different encoding strategies to different parts of the state space. By dividing the state space into manageable ranges and using localized decoding tables for each range, the implementation achieves both high compression ratio and hardware efficiency. Each local region uses optimized operations suitable for hardware implementation.
2Adaptability or versatility
If general-purpose CPU is used for data compression, then flexibility is improved, but hardware efficiency deteriorates
Solution Approach 1:
The patent segments the decoding process into distinct stages: range identification, table lookup, and state update. Each stage can be independently implemented in hardware, allowing parallel processing and efficient resource utilization. The segmentation enables FPGA/ASIC implementation while maintaining the adaptability of ANS encoding.
Solution Approach 2:
The patent introduces decoding tables as intermediary structures that bridge the encoded data and the original symbols. These tables pre-compute transformation relationships, allowing hardware to perform simple lookups rather than complex calculations, thus achieving both efficiency and flexibility.
3Measurement precision
If complex decoding operations are performed, then decoding accuracy is improved, but processing speed deteriorates
Solution Approach 1:
The patent performs preliminary computation by pre-calculating decoding tables that map encoded values to symbols and next states. This preliminary action eliminates the need for complex iterative calculations during actual decoding, allowing hardware to achieve both high accuracy and speed through simple table lookups and direct state updates.
Data Source
AI summary
Systems, apparatus and methods are provided for compressing data and decompressing compressed data. A method may include receiving encoded data to be decompressed, obtaining a size “Stotal” of a total number of symbols in the encoded data, numbers of occurrences for distinct symbols in the encoded data, a number L of sum of the numbers of occurrences for the distinct symbols, and a final state generated during an encoding process as a first state for decoding, building a decoding table containing the distinct symbols corresponding to L encoding states, decoding the encoded data using the decoding table including: obtaining a current symbol from the decoding table based on a current state X, dynamically determining a current number of bits to be recovered from the encoded data and a new state X, and outputting symbols recovered from the encoded data.