ANS Packet Encoding for Run-Length-Limited Clock Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic data communications, clock recovery can fail due to excessively long run lengths of consecutive 1s or 0s, leading to synchronization issues in clock-data recovery processes.
Innovation Solution
Implementing arithmetic coding, specifically Asymmetric Numeral Systems (ANS), to control codewords on a data link, ensuring limited run lengths and balanced signal levels by excluding specific symbols, using a transmitter and receiver configuration with arithmetic decoders and encoders to generate and decode restricted packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If arithmetic coding with symbol exclusion is implemented to limit run lengths, then clock recovery reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the symbol frequency table to set frequencies of excluded symbols to 0, thereby controlling which symbols can appear in the encoded output. This parameter modification enables run length limiting without requiring complex hardware structures, as the same arithmetic coding framework is used but with adjusted frequency parameters that prevent generation of long run-length sequences.
Solution Approach 2:
The patent implements preliminary action by pre-computing and storing the initial state in memory before the encoding process begins. This initial state is derived from the input data packet and is prepared in advance to guide the arithmetic decoder in generating restricted packets that exclude certain symbols. This preparatory step ensures that the encoding process starts with the correct constraints already in place.
2Manufacturing precision
If restricted packets are generated to control signal balance, then synchronization quality is improved, but encoding complexity increases
Solution Approach 1:
The patent achieves universality by using a single arithmetic coding framework that simultaneously performs multiple functions: it encodes the input data while also controlling run lengths and signal balance. The symbol frequency table serves as a universal control mechanism that can exclude different symbols based on the desired constraints, making the same encoder adaptable to various synchronization requirements without needing separate specialized encoders.
Solution Approach 2:
The patent implements feedback through the iterative encoding process where the arithmetic decoder uses the symbol frequency table to determine which symbols are excluded at each encoding step. The encoding process continuously monitors and adjusts symbol selection based on the current state and frequency constraints, ensuring that the output maintains the required signal balance and run length limitations throughout the entire packet.
3Reliability
If arithmetic decoding is used to generate restricted packets, then run length control is achieved, but processing time increases
Solution Approach 1:
The patent replaces traditional mechanical or lookup-table-based encoding methods with arithmetic coding, which uses mathematical operations to generate the encoded output. Instead of using complex combinatorial logic or pre-computed tables for run length limited coding, the system uses arithmetic decoding with modified symbol frequencies, which can be implemented more efficiently using standard arithmetic operations and memory access patterns.
Solution Approach 2:
The patent enables self-service by having the arithmetic decoder automatically adjust its symbol selection based on the frequency table without requiring external intervention or complex control logic. The decoder uses its current state and the frequency information to autonomously determine which symbols to exclude and which to generate, making the run length control inherent to the decoding process itself rather than requiring separate control mechanisms.
Data Source
AI summary
A communication system includes: a transmitter including: an arithmetic decoder configured to generate an output symbol based on input bits and a symbol frequency table that sets frequencies of excluded symbols to 0 and frequencies of allowed symbols to non-zero values, the transmitter being configured to iteratively generate a sequence of restricted packets and an ending state, the sequence of restricted packets excluding instances of the one or more excluded symbols and to transmit the sequence of restricted packets and the ending state on a channel; and a receiver including: an arithmetic encoder configured to compute an output state based on an input state, an input symbol, and the symbol frequency table, the receiver being configured to: supply an ending state received from the channel and the restricted packets to the arithmetic encoder to iteratively generate a final state, and recover a bit sequence from the final state.