Distributed Antenna Data Transport With Scrambling for Clock Sync

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Solution Overview

Problem

Wireless network operators face challenges in managing high data-traffic growth, particularly due to the physical movement of subscribers and increased multimedia content demand, leading to issues with available wireless capacity and data throughput, especially during peak hours when subscribers congregate in large numbers.

Innovation Solution

The implementation of a Distributed Antenna System (DAS) that utilizes a microprocessor or digital components like Field Programmable Gate Array (FPGA) for timing synchronization, employing scrambling and descrambling techniques to maintain clock synchronization in data transmission between host and remote units, ensuring efficient data transport through Digital Access Units (DAUs) and Digital Remote Units (DRUs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If distributed antenna system is deployed to handle high data traffic and subscriber movement, then wireless capacity and data throughput are improved, but clock timing synchronization becomes sensitive to data content and prone to drift

Engineering Contradiction:
Improvedata throughputVSAvoidclock timing synchronization
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A scrambler/descrambler intermediary is introduced between the data source and transmission link. The scrambler modifies the data content before transmission to ensure balanced signal characteristics, while the descrambler restores the original data at the receiver. This intermediary component decouples the transmission link's clock synchronization from the data content, preventing clock drift caused by long runs of zeros or ones.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If digital components like FPGA or microprocessor are used for timing synchronization, then synchronization precision is improved, but device complexity increases

Engineering Contradiction:
Improvetiming synchronization precisionVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces complex digital timing synchronization mechanisms with a simpler signal processing approach. Instead of using microprocessors or FPGAs for clock synchronization, the system uses scrambling/descrambling techniques that operate at the signal level. This substitution eliminates the need for complex digital timing circuits while maintaining synchronization precision through the inherent properties of the scrambled signal.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Ease of manufacture

If network resources are sized for normal working hours subscriber loading, then resource utilization during peak hours is improved, but capacity becomes insufficient during high-traffic periods when subscribers congregate

Engineering Contradiction:
Improvenetwork resource allocationVSAvoidwireless capacity
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The system implements dynamic resource allocation through the distributed antenna architecture, where remote antenna units can be independently activated or deactivated based on real-time traffic demands. The scrambler/descrambler enables efficient data transmission over the digital link connecting these dynamic resources, allowing the network to scale capacity flexibly during high-traffic periods without requiring oversizing during normal operation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11277172B2Digital transport of data over distributed antenna network
Publication Date: 2022.03.15 DALI WIRELESS INC
  • US11277172B2 patent drawing
  • US11277172B2 patent drawing
  • US11277172B2 patent drawing

AI summary

A system for transporting data in a Distributed Antenna System (DAS) includes at least one Digital Access Unit (DAU) and a plurality of Digital Remote Units (DRUs) coupled to the at least one DAU. The plurality of DRUs are operable to transport signals between the plurality of DRUs and the at least one DAU. The at least one DAU includes: a data transport coder comprising: a framer, an encoder, a scrambler, and a serializer and a data transport decoder comprising: a deserializer, a decoder, a descrambler, a frame synchronizer, and a deframer.