Integrated Antenna IC Package With TSV Routing for D-Band Signals
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Solution Overview
Problem
Existing integrated circuit (IC) packages face challenges in efficiently transmitting and receiving high-frequency signals, particularly in the D-band range, while maintaining a small form factor and cost-effective design, especially when antenna, power, and control connections are on the same side of the die or integrated in a single die.
Innovation Solution
The IC package incorporates a semiconductor die with transmitters/receivers configured to transmit and receive signals through an antenna or antenna array on the front side, powered and controlled from the back side via through-substrate vias (TSVs), utilizing a passivation layer and multiple post-passivation interconnect layers to facilitate electrical connections, allowing for a lower cost and smaller form factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If antenna, power, and control connections are integrated in a single die or placed on the same side, then device integration is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the IC package into functionally separate components: the semiconductor die contains only the transmitter/receiver circuitry, while the antenna structure, power connections, and control connections are distributed across multiple layers and substrates. This segmentation reduces the complexity of the die itself while achieving high-level integration through modular assembly.
Solution Approach 2:
The patent transitions from planar integration (all connections on the same side) to three-dimensional integration using stacked layers. The antenna structure is positioned in a second PPI layer above the die, with power and control connections routed through multiple interconnect layers and TSVs, utilizing vertical space to reduce lateral complexity.
2Productivity
If antenna structure is integrated with transmitter/receiver on the same die, then manufacturing steps are reduced, but signal transmission efficiency at high frequencies deteriorates
Solution Approach 1:
The patent separates the antenna structure from the transmitter/receiver die while maintaining electrical connection through controlled impedance traces and interconnect layers. This segmentation allows each component to be optimized independently for its function while preserving signal integrity through careful design of the interconnection path.
Solution Approach 2:
The patent introduces intermediate structures including the passivation layer with openings, conductive traces in PPI layers, and TSVs as mediators to connect the transmitter/receiver on the die to the antenna structure above. These intermediaries are designed to maintain signal integrity while enabling physical separation of components.
3Reliability
If multiple interconnect layers and TSVs are used to connect antenna to transmitter/receiver, then signal transmission efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines multiple manufacturing functions into unified process steps. The formation of TSVs, interconnect layers, and antenna structures is integrated into the existing semiconductor fabrication process flow, utilizing standard deposition, etching, and planarization techniques to reduce overall manufacturing complexity despite the multi-layer structure.
4Ease of manufacture
If traditional single-side connection design is used, then manufacturing is simpler, but form factor and cost are increased
Solution Approach 1:
The patent utilizes vertical stacking to achieve three-dimensional integration, placing the antenna structure above the die rather than requiring lateral expansion. This approach reduces the planar footprint and overall form factor while maintaining manufacturing simplicity through standardized multi-layer fabrication processes.
Data Source
AI summary
An IC package includes a transmitter and/or receiver positioned in a semiconductor die and including a signal terminal, a pad positioned on a first surface of the semiconductor die, the pad being electrically connected to the signal terminal, a passivation layer positioned on the first surface and including a first opening aligned with the pad, a first post-passivation interconnect (PPI) layer including a conductive path electrically connected to the pad, a second PPI layer including an antenna structure electrically connected to the conductive path, and a substrate positioned on a second surface of the semiconductor die opposite the passivation layer, the substrate including a plurality of through-substrate vias (TSVs) electrically coupled to the transmitter and/or receiver.